Semiconductor Package Structure for Stable Redistribution Layers
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Solution Overview
Problem
Current semiconductor packaging methods face challenges in efficiently forming redistribution layers over insulating encapsulants without generating molding pits, which can lead to redistribution layer collapse and reduced yield.
Innovation Solution
A method involving a buffer layer with a de-bonding layer and dielectric layer, through insulator vias, and an insulating encapsulant is used, followed by an isolation layer and redistribution layer formation, allowing for partial encapsulation of semiconductor dies and vias, and enabling electrical connections without the need for extensive grinding or planarization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor packaging methods are used to form redistribution layers over insulating encapsulants, then electrical connections can be established, but molding pits form causing redistribution layer collapse and reduced yield
Solution Approach 1:
The patent applies preliminary action by forming a planarization layer over the insulating encapsulant before forming the redistribution layer. This planarization layer pre-compensates for surface irregularities and prevents molding pit formation that would otherwise cause redistribution layer collapse, thereby improving reliability without sacrificing manufacturing precision
Solution Approach 2:
The patent introduces an intermediary planarization layer between the insulating encapsulant and the redistribution layer. This intermediary layer acts as a mediator that bridges the uneven surface of the encapsulant and the redistribution layer, preventing direct contact between the redistribution layer and molding pits while maintaining proper electrical connections
2Reliability
If extensive grinding or planarization is performed to eliminate molding pits, then redistribution layer collapse is prevented, but fabrication complexity and time increase
Solution Approach 1:
The patent employs a disposable planarization layer that is formed over the insulating encapsulant to provide a planar surface for the redistribution layer. This layer serves its planarization function and can then be removed or left in place, eliminating the need for extensive grinding or planarization processes while maintaining redistribution layer stability, thereby reducing fabrication complexity
3Ease of manufacture
If partial encapsulation of semiconductor dies and vias is implemented, then electrical connections are enabled without extensive grinding, but the encapsulation structure becomes more complex
Solution Approach 1:
The patent applies local quality by providing partial encapsulation of the semiconductor dies and vias rather than complete encapsulation. The insulating encapsulant is formed to encapsulate specific regions where needed while leaving other regions exposed or accessible, enabling electrical connections without extensive grinding or planarization while managing encapsulation structure complexity through selective coverage
Data Source
AI summary
A package structure includes at least one semiconductor die, an insulating encapsulant, an isolation layer and a redistribution layer. The at least one first semiconductor die has a semiconductor substrate and a conductive post disposed on the semiconductor substrate. The insulating encapsulant is partially encapsulating the first semiconductor die, wherein the conductive post has a first portion surrounded by the insulating encapsulant and a second portion that protrudes out from the insulating encapsulant. The isolation layer is disposed on the insulating encapsulant and surrounding the second portion of the conductive post. The redistribution layer is disposed on the first semiconductor die and the isolation layer, wherein the redistribution layer is electrically connected to the conductive post of the first semiconductor die.