Semiconductor Package Redistributing Bonding Pads to JEDEC Standards
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Solution Overview
Problem
As semiconductor packages shrink in size to accommodate more data storage and processing, it becomes challenging to fit a large number of input/output terminals, making it difficult to apply these packages to electronic equipment that adheres to standard JEDEC standards.
Innovation Solution
The semiconductor package integrates multiple semiconductor chips in a matrix form with re-distribution layers and insulation layers to electrically connect bonding pads, allowing for efficient data storage and processing while conforming to JEDEC standards by forming pad parts on the surface of the chips and connecting them through through electrodes or conductive members.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size of the semiconductor package is reduced, then the integration density increases, but the area available for forming input/output terminals decreases
Solution Approach 1:
The patent introduces re-distribution layers that route signals in multiple layers (vertical dimension) rather than only on the surface plane. Through electrodes extend vertically through the package structure, enabling terminals to be formed in three-dimensional space, thereby increasing terminal capacity without proportionally increasing package footprint area.
Solution Approach 2:
Re-distribution layers act as intermediary structures between the bonding pads on the semiconductor chip and the external terminals. These intermediate conductive layers redistribute and extend the terminal connections across multiple locations and layers, effectively multiplying the usable terminal area within the constrained package footprint.
2Quantity of substance
If multiple semiconductor chips are integrated to increase data storage and processing capacity, then the functionality improves, but the device complexity increases
Solution Approach 1:
Multiple semiconductor chips are integrated into a single package structure with unified re-distribution layers and terminal arrangements. The chips are electrically connected through the substrate and re-distribution layers, merging their functionalities while presenting a standardized external interface that conforms to JEDEC standards, thereby managing complexity through integration rather than multiplication of external connections.
Solution Approach 2:
The re-distribution layers serve multiple functions simultaneously: they electrically connect bonding pads across different chips, provide mechanical support, enable signal routing to multiple destinations, and facilitate heat dissipation. This multi-functionality reduces the need for separate dedicated structures for each function, thereby managing overall device complexity.
Data Source
AI summary
The semiconductor package includes: a semiconductor chip module having multiple adjacently arranged or integrally formed semiconductor chips each with a bonding pad group and a connection member electrically connecting each of the bonding pads included in the first bonding pad group to the corresponding bonding pad in the second bonding pad group. In the present invention pad parts can be formed on the outside of the semiconductor chip module to conform with the standards of JEDEC. These pad parts are then connected to the semiconductor chips bonding pads through re-distribution layers. The pad parts of the semiconductor package can then conform to the JEDEC standards even while having a semiconductor chip with bonding pads smaller than the standards.