Semiconductor Package Redistribution Lines Without Plating
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high electrical properties and reliability while maintaining compact size and high performance, particularly in the formation of redistribution lines and under-bump structures.
Innovation Solution
The semiconductor package employs a redistribution line formed through an In-FAB process using deposition and patterning techniques, which includes a metal layer with a hardmask, and an under-bump pattern with a seed layer to enhance structural stability and electrical connectivity, avoiding costly plating processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If plating processes are used to form redistribution lines and under-bump structures, then electrical properties and reliability are improved, but manufacturing cost and equipment investment increase
Solution Approach 1:
The patent changes the manufacturing process parameters from plating-based formation to deposition-based formation of redistribution lines and under-bump structures. This parameter change maintains electrical properties and reliability while reducing equipment investment and manufacturing cost by eliminating the need for expensive plating equipment and processes.
Solution Approach 2:
The patent replaces the mechanical/electrochemical plating system with a deposition-based system. This substitution achieves the same structural formation function (creating conductive pathways and under-bump structures) without requiring plating equipment, thereby reducing manufacturing complexity and cost while maintaining the required electrical properties.
2Reliability
If additional process steps are added to improve electrical properties, then reliability is improved, but manufacturing complexity and time increase
Solution Approach 1:
The patent merges the formation of redistribution lines and under-bump structures into a single deposition-based process flow. By combining these steps and eliminating the separate plating process, the patent reduces fabrication process complexity while maintaining the electrical properties and reliability achieved through traditional multi-step plating processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves electrical properties and reliability of the semiconductor package by ensuring stable connections and reducing the need for additional equipment investment, thus enhancing the overall performance and cost-effectiveness of the fabrication process.
Implementation Method 1
The semiconductor package employs a redistribution line formed through an In-FAB process using deposition and patterning techniques
Data Source
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AI summary
Disclosed is a semiconductor package comprising a semiconductor chip, an external connection member on the semiconductor chip, and a dielectric film between the semiconductor chip and the external connection member. The semiconductor chip includes a substrate, a front-end-of-line structure on the substrate, and a back-end-of-line structure on the front-end-of-line structure. The back-end-of-line structure includes metal layers stacked on the front-end-of-line structure, a first dielectric layer on the uppermost metal layer and including a contact hole that vertically overlaps a pad of an uppermost metal layer, a redistribution line on the first dielectric layer and including a contact part in the contact hole and electrically connected to the pad, a pad part, and a line part that electrically connects the contact part to the pad part, and an upper dielectric layer on the redistribution line.