Semiconductor Package Redistribution Layer with Patterned Insulating Exposed Terminals
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Solution Overview
Problem
Semiconductor packages face challenges in reducing size while maintaining a large number of terminals spaced at a minimum pitch, leading to complications in manufacturing and potential interference between solder balls due to increased terminal density.
Innovation Solution
A semiconductor package design featuring a semiconductor chip with bumps, redistribution layer patterns, a patterned insulating layer, and an encapsulation layer, where conductive particles in an organic insulating layer connect the bumps to the redistribution layer patterns, allowing for a larger pitch between terminals and reducing package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the pitch between terminals is reduced to increase terminal density, then the number of terminals increases, but solder balls may adhere to each other causing manufacturing defects
Solution Approach 1:
The patent transitions from a planar terminal arrangement to a three-dimensional structure by forming terminals that extend through the thickness of the encapsulation layer. This vertical dimension allows terminals to be spaced apart horizontally (maintaining minimum pitch) while still providing multiple connection points, thus increasing terminal density without reducing pitch below minimum values
Solution Approach 2:
The patent embeds multiple terminal structures within the encapsulation layer thickness. Terminals are nested at different depths and positions along the vertical axis, allowing a high number of terminals to be packed into a compact volume while maintaining adequate horizontal spacing to prevent solder ball adhesion
2Adaptability or versatility
If additional wires are added to connect pads to terminals, then terminal connectivity is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent integrates the terminal function and interconnection function into a single structure. The terminals themselves serve as both the external connection points and the internal interconnectors, eliminating the need for separate wire bonding processes. This merging of functions reduces device complexity while maintaining connectivity
Solution Approach 2:
The patent extracts the wire bonding step from the manufacturing process by directly forming conductive terminals within the encapsulation layer. This eliminates the need for separate wire bonding operations, simplifying the manufacturing process while achieving the same connectivity function
3Manufacturing precision
If terminals are extended to the outside of the semiconductor chip, then terminal spacing is improved, but package size increases
Solution Approach 1:
Instead of extending terminals horizontally outside the chip area, the patent utilizes the vertical dimension by forming terminals that extend through the encapsulation layer thickness. This allows adequate terminal spacing to be achieved within the chip footprint, preventing package size increase while maintaining manufacturable pitch
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a compact semiconductor package with a sufficient number of terminals spaced at or above the minimum pitch, facilitating reliable electrical connections without the need for additional wires and simplifying the manufacturing process.
Implementation Method 1
an organic insulating layer interposed between the redistribution layer patterns and the semiconductor chip, having conductive particles distributed in the organic insulating layer. The first parts of the redistribution layer patterns may be electrically connected to the bumps by the conductive particles of the organic insulating layer.
Data Source
AI summary
Provided are a semiconductor package which is small in size but includes a large number of terminals disposed at intervals equal to or greater than a minimum pitch, and a method of fabricating the semiconductor package. The semiconductor package includes a semiconductor chip having a bottom surface on which a plurality of bumps are formed, redistribution layer patterns formed under the semiconductor chip and each including a first part electrically connected to at least one of the bumps and a second part electrically connected to the first part, an encapsulation layer surrounding at least a top surface of the semiconductor chip, and a patterned insulating layer formed below the redistribution layer patterns and exposing at least parts of the second parts of the redistribution layer patterns.