Semiconductor Package with Electroplated Redistribution Layer and Pillars

Solution Overview

Problem

Current power management and semiconductor packaging technologies face challenges with high cost, inferior thermal performance, higher inductance, larger size, and lower integration levels due to the use of lead-frame packages and copper clips, which limit the development of smaller, more efficient electronic devices.

Innovation Solution

A method involving the formation of a redistribution layer and conductive pillars using electroplating processes, coupled with a semiconductor die, and encapsulated within a molding layer to create a more integrated and efficient packaging solution, incorporating passive components like capacitors and inductive components for improved thermal and electrical performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If lead-frame packages and copper clips are used for integration, then device integration is achieved, but cost increases, thermal performance deteriorates, inductance increases, and size increases

Engineering Contradiction:

Improveintegration capabilityVSAvoidmanufacturing cost

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent merges the semiconductor die, capacitive component, and interconnection structures into a single integrated package unit. The die is mounted on a substrate with redistribution layers that directly interconnect to capacitive pads, eliminating the need for separate lead-frames and copper clips. This consolidation achieves device integration while reducing manufacturing cost by simplifying the assembly process and reducing the number of discrete components required.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from planar lead-frame connections to three-dimensional vertical interconnections using conductive pillars and redistribution layers. The capacitive component is positioned in vertical proximity to the die, with electrical connections established through vertically extending conductive structures rather than lateral lead-frame traces. This dimensional change reduces inductance and allows for more compact integration without increasing package footprint.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If lead-frame packages and copper clips are used for integration, then device integration is achieved, but thermal performance deteriorates

Engineering Contradiction:

Improveintegration capabilityVSAvoidthermal performance

Core Design Contradiction:

Adaptability or versatilityVSTemperature

Solution Approach 1:

The patent segments the thermal management function from the electrical interconnection function. Dedicated thermal vias and heat dissipation structures are integrated into the substrate, separate from the signal and power interconnection paths. This allows for optimized thermal conduction pathways that directly conduct heat away from the die without being constrained by the electrical connection requirements of lead-frames, thereby improving thermal performance while maintaining integration capability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The substrate incorporates composite material structures with enhanced thermal conductivity, combining materials that provide both electrical isolation and thermal conduction pathways. The redistribution layers and conductive pillars use material compositions optimized for simultaneous electrical performance and thermal management, creating a multi-functional interconnection system that addresses both electrical integration and thermal dissipation requirements.

Inventive Principle:

Principle #40Composite materials

3Adaptability or versatility

If lead-frame packages and copper clips are used for integration, then device integration is achieved, but inductance increases

Engineering Contradiction:

Improveintegration capabilityVSAvoidelectrical performance

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent transitions from planar lead-frame connections to three-dimensional vertical interconnections using conductive pillars and redistribution layers. The capacitive component is positioned in vertical proximity to the die, with electrical connections established through vertically extending conductive structures rather than lateral lead-frame traces. This dimensional change reduces inductance and allows for more compact integration without increasing package footprint.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The interconnection structures, including redistribution layers and conductive pillars, are pre-formed on the substrate before die mounting. This preliminary formation of low-inductance interconnection paths ensures that when the die is attached, the electrical connections are already optimized for minimal inductance, rather than requiring post-assembly wire bonding or lead-frame attachment that would introduce additional inductance.

Inventive Principle:

Principle #10Preliminary action

4Adaptability or versatility

If lead-frame packages and copper clips are used for integration, then device integration is achieved, but package size increases

Engineering Contradiction:

Improveintegration capabilityVSAvoidpackage size

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent merges the semiconductor die, capacitive component, and interconnection structures into a single integrated package unit. The die is mounted on a substrate with redistribution layers that directly interconnect to capacitive pads, eliminating the need for separate lead-frames and copper clips. This consolidation achieves device integration while reducing manufacturing cost by simplifying the assembly process and reducing the number of discrete components required.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from planar lead-frame connections to three-dimensional vertical interconnections using conductive pillars and redistribution layers. The capacitive component is positioned in vertical proximity to the die, with electrical connections established through vertically extending conductive structures rather than lateral lead-frame traces. This dimensional change reduces inductance and allows for more compact integration without increasing package footprint.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the size and cost of semiconductor packages while enhancing thermal and electrical performance, enabling more integrated and efficient power management systems.

Implementation Method 1

forming a redistribution layer on a substrate using a first electroplating process, and forming a conductive pillar on the redistribution layer using a second electroplating process

Methodology Applied

Scientific EffectElectroplating: Electroplating

Data Source

PatentUS9478519B2Package including a semiconductor die and a capacitive component

Publication Date: 2016.10.25 SEMICON COMPONENTS IND LLC

AI summary

In one general aspect, a method can include forming a redistribution layer on a substrate using a first electroplating process, and forming a conductive pillar on the redistribution layer using a second electroplating process. The method can include coupling a semiconductor die to the redistribution layer, and can include forming a molding layer encapsulating at least a portion of the redistribution layer and at least a portion of the conductive pillar.