Semiconductor Package with Segmented Redistribution Layers
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Solution Overview
Problem
Current semiconductor packaging technologies, such as fan-in and fan-out packages, face challenges in optimizing signal and power characteristics, particularly in high-specification smart electronic devices, where traditional structures struggle to efficiently manage the distribution of I/O terminals and thermal management, leading to spatial limitations and thermal issues.
Innovation Solution
A semiconductor package design featuring a connection structure with redistribution layers, where semiconductor chips and passive components are optimally arranged to create distinct regions for power, ground, and signal patterns, allowing for efficient signal and power distribution and improved thermal management through a frame with integrated wiring layers and stopper layers for heat radiation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional fan-in or fan-out package structures are used, then manufacturing is simpler, but signal and power characteristics are not optimized and spatial limitations occur
Solution Approach 1:
The package structure is divided into distinct regions: a first region with semiconductor chips, a second region with passive components, and a third region as a fan-out area. The connection structure is segmented into multiple redistribution layers (first, second, and third redistribution layers) that independently manage power, ground, and signal distributions. This segmentation allows optimized signal and power characteristics in each region while maintaining overall package functionality.
Solution Approach 2:
The invention transitions from traditional two-dimensional planar arrangements to a three-dimensional stacked configuration with multiple redistribution layers at different heights. The first redistribution layer is disposed at a first height, the second redistribution layer at a second height, and the third redistribution layer at a third height, creating vertical dimensionality that improves signal and power characteristics while managing spatial constraints.
2Adaptability or versatility
If more I/O terminals are distributed to satisfy high specifications, then device performance increases, but thermal management becomes more difficult and spatial constraints worsen
Solution Approach 1:
Different regions of the package are assigned different functional qualities: the first region is optimized for semiconductor chip mounting with appropriate signal routing, the second region is dedicated to passive components with power and ground distribution optimized for that location, and the third region provides fan-out capability. This local optimization allows high I/O terminal distribution while managing thermal characteristics in each specific area.
Solution Approach 2:
The connection structure acts as an intermediary between the semiconductor chips and the external environment, with multiple redistribution layers serving as intermediate connection stages. These intermediary layers provide pathways for signal, power, and ground connections while enabling thermal management through distributed connection points and optimized routing paths that reduce heat concentration.
3Ease of manufacture
If signal patterns are routed through the same region as power patterns, then routing is simpler, but signal integrity deteriorates
Solution Approach 1:
The redistribution layers are segmented into distinct functional zones: power patterns are routed through regions optimized for power distribution, ground patterns through regions optimized for grounding, and signal patterns through regions optimized for signal integrity. This segmentation prevents signal patterns from being routed through regions dominated by power patterns, maintaining signal integrity while keeping the manufacturing process manageable through systematic routing guidelines.
Data Source
AI summary
A semiconductor package includes a first connection structure having a first surface and a second surface and including one or more first redistribution layers, a first semiconductor chip disposed on the first surface, a second semiconductor chip disposed on the second surface, a third semiconductor chip disposed on the second surface, and at least one first passive component disposed between the second and third semiconductor chips on the second surface. The first connection structure may include a first region including a region overlapping the first passive component, and a second region including regions respectively overlapping at least portions of the second and third semiconductor chips, when viewed from above. The first region may be disposed between second regions. The first redistribution may include at least one of a power pattern and a ground pattern in the first region and include a signal pattern in the second region.