Semiconductor Package Redistribution Structure for Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing integration of semiconductor chips leads to higher density of wiring lines, causing issues such as structural instability and electrical reliability concerns in semiconductor packages, particularly due to the complexity of redistribution techniques required for high-speed and compact electronic products.
Innovation Solution
The semiconductor package design incorporates a redistribution structure with specific under-bump patterns and conductive layers, including inclined lateral surfaces and flat top surfaces, to enhance structural stability and electrical properties, and a method of fabrication that forms these patterns to prevent undulation and ensure reliable connections between layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the integration of semiconductor chips is increased, then the compactness and high-speed performance are improved, but the wiring line density increases causing structural instability and electrical reliability issues
Solution Approach 1:
The patent divides the conductive pattern into multiple segments: a first conductive pattern in the first wiring layer and a second conductive pattern in the second wiring layer. This segmentation distributes the wiring density across multiple layers, reducing the burden on any single layer and improving both structural stability and electrical reliability while maintaining high chip integration.
Solution Approach 2:
The patent transitions from planar wiring to three-dimensional multi-layer wiring structure. By adding vertical dimension with multiple wiring layers stacked at different heights, the patent achieves higher integration without proportionally increasing wiring density in any single plane, thus maintaining reliability.
2Productivity
If the integration of semiconductor chips is increased, then the compactness and high-speed performance are improved, but the wiring line density increases causing structural instability
Solution Approach 1:
The conductive wiring structure is segmented into multiple layers with distinct functions. The first conductive pattern handles certain signal routes while the second conductive pattern handles other routes, distributing mechanical stress and improving structural stability despite high integration density.
Solution Approach 2:
The patent employs a composite wiring structure with conductive patterns embedded in dielectric layers. This composite architecture combines the electrical conductivity of metal patterns with the mechanical support of dielectric materials, enhancing overall structural stability while enabling high integration.
3Device complexity
If redistribution technique is simplified, then the manufacturing complexity is reduced, but the electrical properties and drive reliability deteriorate
Solution Approach 1:
The multi-layer conductive pattern structure serves multiple functions simultaneously: it provides electrical connectivity, enables signal redistribution, and maintains structural integrity. This universal design achieves reliable drive performance without requiring overly complex manufacturing processes.
Solution Approach 2:
The patent optimizes parameters such as the spacing between conductive patterns, the thickness of dielectric layers, and the configuration of wiring routes. By carefully adjusting these parameters, the patent achieves reliable electrical properties while keeping the manufacturing process manageable.
Data Source
AI summary
Disclosed are semiconductor packages and fabrication methods thereof. The semiconductor package may include a lower substrate, a lower semiconductor chip, a redistribution layer, an upper semiconductor chip, and a through electrode. The lower substrate may include a first dielectric layer, a first conductive pattern having a wiring pattern and an under-bump pattern, a second dielectric layer, and a second conductive pattern. The under-bump pattern may include a first head part and a first tail part. The first head part may have a first lateral surface on the first dielectric layer that is inclined to a top surface of the first dielectric layer. The second conductive pattern may have a second lateral surface on the second dielectric layer that is perpendicular to a top surface of the second dielectric layer.