Semiconductor Package Structure With Outer Conductive Vias
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Solution Overview
Problem
Existing semiconductor package structures face challenges with high die attach accuracy requirements, long electrical routing paths, increased thickness due to micro bumps or solder balls, warpage issues, and limited interconnection density, leading to poor electrical properties and reliability.
Innovation Solution
A semiconductor package structure that combines semiconductor dies and redistribution layers into a module, embedded in a protection layer with outer conductive vias, eliminating the need for micro bumps or solder balls, and using a wiring structure with dielectric and redistribution layers to reduce thickness and enhance interconnection density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flip chip bonding with micro bumps is used to connect semiconductor die, then electrical connection is achieved, but die attach accuracy requirement becomes very high and cycle time increases
Solution Approach 1:
The patent segments the connection structure by replacing the traditional micro bump connection between semiconductor die with a redistribution layer-based connection. The semiconductor die is connected to the package substrate through a redistribution layer that routes signals laterally, avoiding the need for precise micro bump alignment. This segmentation of the electrical connection path eliminates the high die attach accuracy requirement while maintaining reliable electrical connection and enabling faster cycle times.
2Adaptability or versatility
If interconnection solder balls are used to connect two semiconductor packages, then package on package structure is formed, but overall thickness of the semiconductor package structure increases
Solution Approach 1:
The patent extracts and eliminates the interconnection solder balls from the package structure. Instead of using solder balls to connect two semiconductor packages vertically, the invention uses a redistribution layer that routes electrical connections laterally within the package substrate. This extraction of the solder ball component significantly reduces the overall thickness of the semiconductor package structure while maintaining the package on package capability through alternative electrical interconnection paths.
3Reliability
If micro bumps or solder balls are used for interconnection, then electrical connection is achieved, but interconnection density is limited and electrical properties deteriorate
Solution Approach 1:
The patent transitions from vertical interconnection (micro bumps and solder balls extending in the thickness direction) to lateral interconnection through the redistribution layer. By routing electrical connections in the planar dimension rather than the vertical dimension, the invention achieves higher interconnection density and improved electrical properties. The redistribution layer provides multiple signal paths and shorter connection lengths, enhancing electrical performance while increasing the number of possible interconnections within the same footprint.
Data Source
AI summary
A semiconductor package structure includes a wiring structure, a semiconductor module, a protection layer and a plurality of outer conductive vias. The wiring structure includes at least one dielectric layer and at least one redistribution layer. The semiconductor module is electrically connected to the wiring structure. The semiconductor module has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The protection layer covers the lateral surface of the semiconductor module and a surface of the wiring structure. The outer conductive vias surround the lateral surface of the semiconductor module, electrically connect to the wiring structure, and extend through a dielectric layer of the wiring structure and the protection layer.