Semiconductor Package Design for Reduced Input Capacitance
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Solution Overview
Problem
The increasing demand for higher-performance, faster-speed, and smaller-sized semiconductor components leads to increased input capacitance when memory chips are stacked, resulting in decreased speed and a complex die bonding and wire bonding process.
Innovation Solution
A semiconductor package design featuring a package substrate with a first semiconductor chip and second semiconductor chips stacked on both sides, where the first chip includes peripheral circuits to drive memory cells in the second chips, and the chips are electrically connected through wires or conductive patterns, reducing input capacitance by separating cell array and peripheral circuit regions into different chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory chips are stacked on a single package substrate, then the storage capacity is increased, but the input capacitance increases and speed decreases
Solution Approach 1:
The patent divides the semiconductor chip into two separate functional chips: a first chip containing only the cell array region (memory cells) and a second chip containing only the peripheral circuit region (driving circuits). This segmentation allows the memory cells to be stacked vertically while the peripheral circuits remain on a separate chip, reducing the input capacitance at the signal input terminals and improving signal transmission speed.
2Quantity of substance
If multiple memory chips are stacked on a single package substrate, then the storage capacity is increased, but the die bonding and wire bonding processes become complex
Solution Approach 1:
By segmenting the chip into cell array and peripheral circuit regions that are manufactured separately and then bonded together, the patent simplifies the overall process. Each chip can be optimized and tested independently before final assembly, reducing the complexity of continuous repeated bonding operations required for stacking multiple complete memory chips.
3Ease of manufacture
If cell array and peripheral circuit are integrated in the same chip, then the manufacturing process is simpler, but the input capacitance increases
Solution Approach 1:
The patent separates the cell array and peripheral circuit onto different chips, with the cell array chip being stacked on the peripheral circuit chip. This segmentation reduces the input capacitance because the signal input terminals are only connected to the peripheral circuit chip, not to multiple cell array chips. The manufacturing complexity is managed through standardized bonding processes between the two chip types.
Data Source
AI summary
Provided is a semiconductor package in which a cell array region and a peripheral circuit region are formed as different semiconductor chips, respectively. First semiconductor chips including memory cells and a second semiconductor chip including only peripheral circuitry common to the first semiconductor chips are electrically connected to each other. Thus, a loading capacitance of the semiconductor package may be reduced. As a result, an RC delay of the semiconductor package may be reduced, thereby improving an operating speed of the semiconductor package.