Semiconductor Package Self-Alignment via Reflowed Solder Bumps

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Solution Overview

Problem

The challenge is to create a semiconductor package structure with high accuracy and yield, effective heat dissipation, and cost-effective fabrication, while ensuring precise alignment and efficient heat transfer, particularly for high-density input/output terminals in compact designs.

Innovation Solution

A semiconductor package structure featuring a base substrate with a heat dissipation plug and solder bumps, where the solder bumps are reflowed to self-align the die on the substrate, allowing for efficient heat dissipation and signal transmission with anti-parallel directions, and a method involving a re-distribution layer and solder balls for interconnection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If solder bumps are reflowed to self-align the die on the substrate, then manufacturing precision is improved, but device complexity increases due to additional thermal management components

Engineering Contradiction:
Improvealignment accuracyVSAvoidstructure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The solder bumps serve dual functions: electrical connection between die and substrate, and thermal conduction path for heat dissipation. The patent integrates heat dissipation functionality into the existing solder bump structure, eliminating the need for separate thermal management components while maintaining alignment precision through the reflow process

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines multiple functions (electrical connection, thermal management, and mechanical alignment) into a single integrated structure. The solder bumps are designed to simultaneously provide electrical connectivity, heat conduction, and self-alignment during the reflow process, reducing overall device complexity

Inventive Principle:
Principle #5Merging (Combining)

2Temperature

If heat dissipation plug is added to the substrate, then heat dissipation efficiency is improved, but manufacturing cost increases

Engineering Contradiction:
Improveheat dissipation efficiencyVSAvoidfabrication cost
Core Design Contradiction:
TemperatureVSEase of manufacture

Solution Approach 1:

The substrate is designed with multi-functionality, serving both as the mechanical support platform and as a heat dissipation structure. The heat dissipation plug is integrated into the substrate structure, allowing the substrate to perform both structural and thermal management functions, thereby avoiding additional manufacturing costs for separate components

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent employs composite material structures in the substrate design, combining materials with different thermal and mechanical properties. The heat dissipation plug uses materials optimized for thermal conduction, while the surrounding substrate provides mechanical support, creating a cost-effective composite structure that addresses both structural and thermal requirements

Inventive Principle:
Principle #40Composite materials

3Adaptability or versatility

If high density patterns are formed for many input/output terminals, then functionality is improved, but manufacturing precision requirements become more stringent

Engineering Contradiction:
Improveinput/output terminal densityVSAvoidpattern alignment accuracy
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The solder bumps perform self-alignment during the reflow process through surface tension and capillary forces, automatically positioning the die relative to the substrate without requiring external alignment mechanisms. This self-service alignment mechanism ensures high precision for high-density patterns while simplifying the manufacturing process

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent utilizes parameter changes during the reflow process, specifically the phase transition of solder from solid to liquid and back, to achieve precise alignment. The melting and solidification of solder bumps create controlled thermal and mechanical conditions that enable sub-micron alignment accuracy for high-density interconnect patterns

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances fabrication yield, reduces costs, and provides a high heat-dissipating property, enabling precise alignment and efficient heat transfer, even in compact designs, without the need for additional heat sinks or thermal interface materials.

Implementation Method 1

when temperature of the melted solder is returned to a room temperature, thereby allowing the die to be formed on the substrate with a high positional accuracy

Methodology Applied
Scientific EffectThermal contraction: Thermal Contraction

Implementation Method 2

a heat dissipation plug, which discharges heat generated in the die to the outside

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS10847435B2Semiconductor package structure and fabrication method thereof
Publication Date: 2020.11.24 SAMSUNG ELECTRONICS CO LTD
  • US10847435B2 patent drawing
  • US10847435B2 patent drawing
  • US10847435B2 patent drawing

AI summary

A method of fabricating a semiconductor package structure is provided. The structure is configured to include a base substrate, a die disposed on the base substrate, the die including a semiconductor device, a solder bump disposed on a surface of the die, and configured to discharge heat generated in the die to an outside; and a solder ball disposed on another surface, opposite to the surface, of the die, and configured to transmit a signal, which is produced by the semiconductor device of the die, to an external device.