Semiconductor Package Reinforcing Wiring Warpage Reduction
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Solution Overview
Problem
Semiconductor packages experience warpage due to differences in thermal expansion coefficients and Young's modulus between the semiconductor chip and the insulating and wiring layers, leading to deformation and instability.
Innovation Solution
A semiconductor package design where a reinforcing wiring pattern with a thermal expansion coefficient between that of the semiconductor chip and the wiring layers is integrated on the side of the package not embedding the chip, balancing physical property values and reducing warpage through the use of a 42 alloy with a thermal expansion coefficient of approximately 4.5 ppm/°C, which is closer to the chip's 3.4 ppm/°C silicon and the wiring layers' 17.2 ppm/°C copper.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the semiconductor chip is embedded in only one side of the first insulating layer, then the manufacturing process is simplified, but warpage occurs due to imbalance in physical properties
Solution Approach 1:
The patent applies asymmetry by creating an intentional imbalance in the physical properties of layers on opposite sides of the insulating layer. Specifically, a reinforcing wiring pattern with thermal expansion coefficient between that of the semiconductor chip (3.4 ppm/°C) and the wiring layer (17.2 ppm/°C) is formed on the side opposite to the embedded chip. This asymmetric configuration of material properties balances the overall physical characteristics, preventing warpage while maintaining the simplified single-sided embedding process.
2Ease of manufacture
If the thermal expansion coefficient difference between materials is large, then material selection is easier, but thermal stress and deformation increase
Solution Approach 1:
The patent applies parameter changes by carefully selecting and controlling the thermal expansion coefficient of the reinforcing wiring pattern material. The thermal expansion coefficient is set to an intermediate value between the semiconductor chip (3.4 ppm/°C) and the wiring layer (17.2 ppm/°C), creating a gradient that reduces thermal stress. This parameter optimization allows for easier material selection while minimizing thermal stress and deformation in the package structure.
3Stability of the object's composition
If the first insulating layer side is made rigid to prevent deformation, then the chip side stability is improved, but the other side becomes more prone to warpage
Solution Approach 1:
The patent applies the counterweight principle by introducing a reinforcing wiring pattern on the side opposite to the embedded semiconductor chip. This reinforcing structure acts as a counterbalance to the rigid first insulating layer, compensating for the imbalance in physical properties. The reinforcing wiring pattern, with its intermediate thermal expansion coefficient, provides structural support that prevents warpage while maintaining chip side stability, effectively balancing the overall package geometry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively prevents warpage and improves the stiffness of the semiconductor package by aligning the thermal expansion coefficients and Young's modulus of the wiring pattern with the chip, ensuring stability and reducing deformation under thermal stress.
Implementation Method 1
A thermal expansion coefficient of a main component of the reinforcing wiring pattern is between a thermal expansion coefficient of a main component of the wiring layer of the wiring structure and a thermal expansion coefficient of a main component of the semiconductor chip
Data Source
AI summary
A semiconductor package includes: a semiconductor chip: a first insulating layer, wherein the semiconductor chip is embedded in the first insulating layer such that the first surface and the side surface of the semiconductor chip are covered by the first insulating layer; a wiring structure on the first surface of the first insulating layer and comprising an insulating layer and a wiring layer; an outermost wiring layer on the wiring structure and having: a reinforcing wiring pattern; and a via wiring which penetrates the reinforcing wiring pattern and electrically connected to the reinforcing wiring pattern, wherein the via wiring is formed through the insulating layer of the wiring structure and electrically connected to the wiring layer of the wiring structure; a second insulating layer on the wiring structure to cover the outermost wiring layer.