Semiconductor Package Relay-Pad Layout for Compact SiC Modules
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Solution Overview
Problem
Existing semiconductor packages for power semiconductor devices, such as MOSFET modules using silicon carbide (SiC), face challenges in increasing current capacity and size due to complex assembly methods and insulation requirements, leading to larger device sizes and increased costs.
Innovation Solution
A semiconductor package design featuring a conductor substrate with bonded semiconductor elements and a wiring element that includes relay pads and wiring portions, allowing for efficient connection and insulation, reducing the number of relay pads and optimizing wire connections to minimize size and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If signal wiring pattern and main current circuit pattern are arranged on the same member, then assembly is simplified, but insulation difficulty increases requiring larger spacing and larger device size
Solution Approach 1:
The patent divides the wiring functions into separate members: the insulating substrate carries signal wiring patterns, while the conductor substrate carries main current circuit patterns. This segmentation isolates high-voltage current paths from low-voltage signal paths, eliminating insulation spacing requirements between them while simplifying assembly procedures.
2Reliability
If sufficient spacing is provided between signal wiring pattern and main current circuit pattern for insulation, then insulation reliability is improved, but device size increases
Solution Approach 1:
By segmenting the wiring patterns onto separate substrates (insulating substrate for signals, conductor substrate for currents), the patent eliminates the need for insulation spacing between signal and current paths on the same plane, thereby reducing device area while maintaining insulation reliability through physical separation of the substrates themselves.
Solution Approach 2:
The patent transitions from a two-dimensional layout where signal and current patterns coexist on the same plane to a three-dimensional arrangement where they are separated vertically across different substrates. This dimensional change allows compact packaging without compromising insulation, as the substrates can be bonded face-to-face with minimal spacing.
3Power
If complex assembly method is used to connect multiple semiconductor chips in parallel, then current capacity is increased, but manufacturing cost increases
Solution Approach 1:
The patent merges multiple semiconductor chips onto a single conductor substrate where they share common current circuit patterns and bonding structures. This consolidation allows parallel current paths to be established through the substrate itself rather than requiring complex external wiring and assembly procedures, thereby reducing manufacturing cost while maintaining high current capacity.
Data Source
AI summary
An object is to provide technology that enables cost reduction or downsizing of semiconductor packages. The wiring element includes a second substrate, a plurality of first relay pads arranged on a surface of the second substrate opposite to the conductor substrate and connected to each of the control pads of the plurality of semiconductor elements by wires, a plurality of second relay pads arranged on the surface of the second substrate opposite to the conductor substrate, the number thereof being equal to or lower than the number of the plurality of first relay pads, and a plurality of wiring portions arranged on the surfaceof the second substrate opposite to the conductor substrate and selectively connecting the plurality of first relay pads and the plurality of second relay pads.