Semiconductor Package Build-Up Process Resin Polishing

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Solution Overview

Problem

Existing semiconductor package manufacturing methods face challenges such as electrical connection errors due to resin entering between pads and wiring layers, difficulty in controlling resin amount, and the semiconductor package's tendency to bend during the build-up process, as well as limitations in reducing the thickness of the insulating layer.

Innovation Solution

A method involving a supporting substrate with a fixing material, where a semiconductor chip is mounted with its active surface facing upwards, an encapsulation resin layer is formed to cover the chip, and the top surface of the resin layer is polished to expose the pad surfaces, allowing for precise formation of thin wiring and insulating layers, preventing resin from interfering with electrical connections and reducing the package's thickness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If the supporting substrate and fixing material are kept during the build-up process, then the semiconductor package maintains structural stability, but the package thickness increases and heat dissipation is reduced

Engineering Contradiction:
Improveheat dissipationVSAvoidpackage thickness
Core Design Contradiction:
TemperatureVSLength of stationary object

Solution Approach 1:

The patent applies preliminary action by mounting the semiconductor chip on a temporary supporting substrate with fixing material before the build-up process, then removing them after encapsulation and wiring are complete. This allows the chip to be stable during manufacturing but enables thin final packaging for heat dissipation.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If the encapsulation resin layer is formed without polishing, then the manufacturing process is simpler, but the pad surface cannot be exposed and electrical connections are compromised

Engineering Contradiction:
Improvepad exposure precisionVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by forming the encapsulation resin layer to cover the chip and pads, then selectively removing resin through polishing to expose pad surfaces. This preliminary encapsulation protects the chip during manufacturing while controlled removal enables precise pad exposure for electrical connections.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If resin is applied generously to ensure complete coverage, then the chip is well protected, but resin enters between pads and wiring layers causing electrical connection errors

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidresin amount control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by first forming the encapsulation resin layer to cover the chip and pads completely, then selectively removing resin from pad areas through polishing. This ensures adequate protection during manufacturing while preventing resin interference with electrical connections.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies local quality by differentiating the treatment of different areas: the encapsulation resin covers the chip body for protection, but is selectively removed from pad surfaces to expose them for electrical connections. This localized differentiation ensures both protection and connectivity.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach ensures accurate electrical connections, prevents package bending, and allows for the manufacture of thinner semiconductor packages with improved heat dissipation properties by removing the supporting substrate and fixing material, thereby enhancing the precision and stability of the build-up process.

Implementation Method 1

polishing the encapsulation resin layer to expose a top surface of the pad

Methodology Applied
Scientific EffectPolishing: Abrasion

Data Source

PatentUS8785256B2Method of manufacturing semiconductor package
Publication Date: 2014.07.22 SHINKO ELECTRIC IND CO LTD
  • US8785256B2 patent drawing
  • US8785256B2 patent drawing
  • US8785256B2 patent drawing

AI summary

There is provided a method of manufacturing a semiconductor package. The method includes: (a) providing a semiconductor chip having a first surface and a second surface opposite to the first surface, wherein a pad is formed on the first surface; (b) disposing the semiconductor chip on a supporting substrate such that the first surface is directed upward; (c) forming an encapsulation resin layer on the supporting substrate so as to cover the semiconductor chip; and (d) polishing the encapsulation resin layer to expose a top surface of the pad.