Semiconductor Package Rewiring Layout for Lower-Cost High-Yield Packaging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor packaging technologies, such as Fan-Out Wafer-Level Packaging (FOWLP), face challenges in reducing production costs while maintaining high precision and yield, due to high material usage and potential for fabrication errors leading to waste and reduced yield.
Innovation Solution
The method involves fabricating semiconductor packages using a combination of wafer-level and panel-level processes, where high-precision first rewiring layers are formed on a substrate, followed by the addition of low-precision second rewiring layers connected through an encapsulation layer, allowing for increased wafer utilization and error adjustment, thereby reducing costs and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If FOWLP technology is used to achieve high precision and reliability, then manufacturing precision and reliability are improved, but production cost increases and productivity decreases
Solution Approach 1:
The patent divides the rewiring structure into multiple separate rewiring layers (first rewiring layer, second rewiring layer, third rewiring layer) that are formed at different stages. This segmentation allows each layer to be optimized independently and enables parallel processing of different layers, thereby improving both precision and productivity without being constrained by the limitations of traditional FOWLP technology.
2Manufacturing precision
If FOWLP technology is used to achieve high precision packaging, then manufacturing precision is improved, but production cost increases
Solution Approach 1:
The patent forms the first rewiring layer on the wafer before the semiconductor elements are mounted. This preliminary action allows the rewiring structure to be prepared in advance with high precision using wafer-level processing, while the subsequent mounting and additional rewiring layers can be performed separately. This approach eliminates the need for expensive and time-consuming rework if errors occur, thereby reducing overall production cost while maintaining high precision.
Solution Approach 2:
The patent changes the precision requirements for different rewiring layers. The first rewiring layer formed on the wafer requires high precision, while the second and third rewiring layers formed after mounting can have lower precision requirements. This parameter change allows the use of less expensive manufacturing processes for the later layers, reducing overall production cost while still achieving the required final packaging precision.
3Reliability
If traditional packaging methods are used, then fabrication errors may occur leading to waste, but material utilization is low and yield is reduced
Solution Approach 1:
The patent forms the first rewiring layer on the wafer before mounting the semiconductor elements. This preliminary action allows for early detection and correction of fabrication errors while the entire wafer is still available for rework. If errors are detected, the wafer can be reprocessed without wasting the expensive semiconductor elements, thereby improving yield and reducing material loss.
Solution Approach 2:
The patent creates a modular structure where the first rewiring layer is formed on the wafer before element mounting, providing a cushioning effect that isolates the expensive semiconductor elements from potential fabrication errors in the rewiring process. This modular approach ensures that errors in the rewiring layers do not necessarily lead to waste of the semiconductor elements, thereby protecting the investment in high-value components.
Data Source
AI summary
Provided are a semiconductor package and a method for fabricating the semiconductor package. The method includes the followings steps: a first workpiece is provided, where the first workpiece includes a first substrate and multiple first rewiring structures arranged on the first substrate at intervals, and each first rewiring structure includes at least two first rewiring layers; an encapsulation layer is formed on the first rewiring structures, where the encapsulation layer is provided with multiple first through holes, and the first through holes expose one first rewiring layer; at least two second rewiring layers are disposed on a side of the encapsulation layer facing away from the first rewiring layer; multiple semiconductor elements are provided, where the semiconductor elements are arranged on a side of the first rewiring structures facing away from the encapsulation layer, where the first rewiring layers are electrically connected to pins of the semiconductor elements.