Semiconductor Package Bump Layout for RF Signal Isolation
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Solution Overview
Problem
In semiconductor packages handling high-frequency signals, reducing the size while maintaining high-frequency characteristics poses a challenge, as simply reducing the pitch of solder bumps can lead to signal leakage between bumps and the IC chip.
Innovation Solution
The semiconductor package design includes RF bumps overlapping mold resin and GND bumps positioned on the shortest line segment connecting the RF bumps and IC chip, with GND bumps acting as a wall to limit signal leakage, and RF bumps disposed at the outermost edge, surrounded by GND bumps, with rewiring configurations that enhance isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the pitch of solder bumps is reduced to decrease package size, then the package size is reduced, but high-frequency signal leakage to other contacts through the IC chip increases
Solution Approach 1:
A ground bump is introduced as an intermediary element between the RF bump and the IC chip. This ground bump acts as a mediator that blocks the direct coupling path for high-frequency signals, preventing signal leakage while allowing the pitch to be reduced for compact packaging.
Solution Approach 2:
The space between the RF bump and the IC chip is segmented by introducing a ground bump. This segmentation divides the electromagnetic field distribution and creates isolation regions, preventing the high-frequency signal from propagating directly through the IC chip to adjacent contacts.
2Volume of moving object
If the pitch of solder bumps is reduced to decrease package size, then the package size is reduced, but isolation between RF bump and IC chip deteriorates
Solution Approach 1:
The ground bump serves as a shielding intermediary that maintains electrical isolation between the RF bump and the IC chip even when the pitch is reduced. This intermediary structure preserves the isolation performance by providing a reference potential barrier that prevents capacitive coupling of high-frequency signals.
3Object-generated harmful factors
If GND bump is positioned on the shortest line segment connecting RF bump and IC chip, then signal leakage is reduced, but device complexity increases
Solution Approach 1:
The ground bump is strategically positioned only at the critical location on the shortest line segment between the RF bump and the IC chip, where signal leakage is most severe. This localized approach provides effective shielding exactly where needed without requiring a complex overall bump pattern, thus minimizing the increase in device complexity.
Data Source
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AI summary
A semiconductor package (1) includes an IC chip (10); a mold resin (20) surrounding the IC chip (10) in plan view; an insulating layer formed on one surface of the IC chip (10) and the mold resin (20); a plurality of solder bumps (50) formed on the insulating layer; and a rewiring (40) formed on the insulating layer and connecting the IC chip (10) to the plurality of solder bumps (50), in which the plurality of solder bumps (50) include an RF bump (51) through which a high-frequency signal passes, and a GND bump (52) electrically grounded, and the RF bump (51) is disposed at a position overlapping the mold resin (20) in plan view, and the GND bump (52) is disposed on a shortest line segment (L3, L4) connecting the RF bump (51) and the IC chip (10) in plan view.