Semiconductor Package Routing Distance Reduction
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Solution Overview
Problem
The semiconductor industry faces challenges in integrating high-functional electronic components into small packages while maintaining high performance and low cost, particularly in reducing the distance between semiconductor devices and integrated passive devices to improve electrical performance.
Innovation Solution
A device package structure is formed with a redistribution structure over a carrier substrate, an integrated passive device attached between the redistribution structure and an interconnect structure, and a semiconductor device attached to the redistribution structure, reducing the distance between the semiconductor device and the integrated passive device, thereby improving electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If integrated circuits are packaged with traditional wiring layouts, then package area is reduced, but routing distance and inductance increase degrading electrical performance
Solution Approach 1:
The patent implements fan-out wiring that extends connections from the chip surface into the package substrate, utilizing the third dimension (depth) to route signals. This dimensional transition allows electrical contacts to be made at a larger pitch on the package surface while maintaining short routing distances through vertical vias and redistributed layers, thereby reducing inductance and improving electrical performance.
Solution Approach 2:
The patent introduces a redistribution layer (RDL) as an intermediary structure between the chip contact pads and the package external contacts. This RDL acts as a mediator that fans out the wiring, allowing signals to be redistributed to larger pitch locations while maintaining short electrical paths through controlled impedance routing and via connections, thus reducing overall routing distance and inductance.
2Adaptability or versatility
If more input/output pads are integrated to increase functionality, then device complexity increases, but package area must increase
Solution Approach 1:
The patent creates a universal package structure with a redistribution layer that can accommodate multiple input/output pads with different routing requirements. The RDL design allows the same package structure to handle various signal types (power, ground, data, control) through a unified fan-out architecture, enabling high functionality without proportionally increasing package area.
Solution Approach 2:
By transitioning from planar 2D routing to 3D fan-out routing with multiple redistribution layers and vertical vias, the patent enables more I/O pads to be accommodated within the same package footprint. The vertical dimension provides additional routing space, allowing signals to be redistributed to larger pitch locations, thus increasing functionality without proportionally increasing package area.
Data Source
AI summary
A method includes forming a redistribution structure on a carrier, attaching an integrated passive device on a first side of the redistribution structure, attaching an interconnect structure to the first side of the redistribution structure, the integrated passive device interposed between the redistribution structure and the interconnect structure, depositing an underfill material between the interconnect structure and the redistribution structure, and attaching a semiconductor device on a second side of the redistribution structure that is opposite the first side of the redistribution structure.