Semiconductor Package Routing Via Structure for High-Aspect Through Holes
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Solution Overview
Problem
The integration of multiple semiconductor devices in wafer-level packaging poses challenges due to the complexity of forming efficient and reliable interconnects through high-aspect-ratio through holes in substrates, which affects the yield and cost-effectiveness of semiconductor packages.
Innovation Solution
A method involving dual-side sputtering of composite seed-barrier layers within high-aspect-ratio through holes in substrates, where one side is masked as blind holes, allows for asymmetrical redistribution structures and reduces material diffusion, enabling efficient electrical connections and adhesion without requiring double-side plating tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual-side plating tools are used to form interconnects through high-aspect-ratio through holes, then electrical connection reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The through hole formation process is segmented into two stages: first forming blind holes from the first surface to a predetermined depth, then completing the through holes by removing the mask layer and continuing etching from the second surface. This segmentation allows each etching operation to work with lower aspect ratios, improving reliability while simplifying equipment requirements compared to forming complete through holes in a single step.
Solution Approach 2:
The mask layer is applied and preliminary etching to create blind holes is performed before the through holes are completed. This preliminary action establishes the initial hole structure and positioning, allowing subsequent completion steps to focus only on penetrating through the substrate rather than creating the entire hole structure, thereby reducing the complexity of the equipment needed.
2Productivity
If high-aspect-ratio through holes are formed in substrates, then interconnect density is improved, but manufacturing difficulty and cost increase
Solution Approach 1:
The formation of high-aspect-ratio through holes is segmented into two phases: first creating blind holes with lower aspect ratios from the first surface, then completing the holes from the second surface after mask removal. This segmentation reduces the maximum aspect ratio each etching process must achieve, making manufacturing easier while maintaining high interconnect density.
Solution Approach 2:
The etching process applies different conditions to different regions: blind holes are etched from the first surface with specific depth control, while the completion etching from the second surface targets only the remaining substrate thickness. This local quality approach optimizes each etching operation for its specific task, reducing overall manufacturing difficulty.
3Ease of manufacture
If material diffusion is not controlled in through holes, then manufacturing process simplicity is maintained, but adhesion and electrical connection quality deteriorate
Solution Approach 1:
A barrier layer is introduced as an intermediary between the conductive material and the substrate walls in the through holes. This barrier layer prevents unwanted material diffusion while maintaining adhesion and electrical connection quality, and can be selectively removed in certain regions to enable proper electrical connections without complicating the overall process.
Solution Approach 2:
The barrier layer is applied uniformly but selectively removed in specific regions where electrical connections are needed. This local quality approach maintains adhesion and prevents diffusion in regions where it is needed, while allowing proper electrical contact in connection regions, balancing process simplicity with connection quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the adhesion and reduces material diffusion, allowing for lower resistance electrical connections and improved yield by enabling single-side plating and reducing operational costs through efficient substrate utilization.
Implementation Method 1
A first barrier material is sputtered on the substrate, from the side of the first surface. A first seed material is sputtered on the first barrier material. A second conductive material is plated on an opposite side of the first seed material with respect to the first conductive material.
Data Source
AI summary
Semiconductor package includes substrate, first barrier layer, second barrier layer, routing via, first routing pattern, second routing pattern, semiconductor die. Substrate has through hole with tapered profile, wider at frontside surface than at backside surface of substrate. First barrier layer extends on backside surface. Second barrier layer extends along sidewalls of through hole and on frontside surface. Routing via fills through hole and is separated from sidewalls of through hole by at least second barrier layer. First routing pattern extends over first barrier layer on backside surface and over routing via. First routing pattern is electrically connected to end of routing via and has protrusion protruding towards end of routing via in correspondence of through hole. Second routing pattern extends over second barrier layer on frontside surface. Second routing pattern directly contacts another end of routing via. Semiconductor die is electrically connected to routing via by first routing pattern.