Semiconductor Package Insulating Layer Segmentation for Sawing Reliability
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Solution Overview
Problem
Current semiconductor packages with vertically stacked chips face challenges in miniaturization and high performance due to limitations in packaging design and manufacturing processes, particularly in separating and protecting the inter-wiring insulating layers during the sawing process, which can lead to reliability issues and increased manufacturing costs.
Innovation Solution
The semiconductor package incorporates a modified layer formed by carbonizing a portion of the inter-wiring insulating layer using laser light, creating a carbonized material that separates the main and edge regions of the inter-wiring insulating layer, thereby preventing peeling and simplifying the manufacturing process while enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the inter-wiring insulating layer is separated into main and edge regions during the sawing process, then the reliability of the semiconductor package is improved, but the manufacturing complexity and cost increase
Solution Approach 1:
The inter-wiring insulating layer is segmented into a main region (first region) and an edge region (second region) that are spatially separated. This segmentation allows the main region to maintain electrical insulation functionality while the edge region can be removed or modified during sawing, preventing peeling and improving reliability without requiring complex additional structures
Solution Approach 2:
The inter-wiring insulating layer is pre-formed with distinct main and edge regions before the sawing process. This preliminary structuring ensures that when sawing occurs, the edge region can be properly managed (removed or protected) to prevent peeling of the main region, thereby improving reliability without adding manufacturing complexity
2Ease of manufacture
If the inter-wiring insulating layer is kept intact during manufacturing, then the manufacturing process is simplified, but peeling occurs during sawing which reduces reliability
Solution Approach 1:
The inter-wiring insulating layer is divided into main and edge regions, allowing the bulk of the layer (main region) to remain intact and simple to manufacture, while only the edge portion requires special handling. This segmentation resolves the contradiction by maintaining manufacturing simplicity for the majority of the structure while addressing reliability concerns at critical edges
Solution Approach 2:
Different regions of the inter-wiring insulating layer are given different treatments: the main region maintains its standard insulating properties and structure for ease of manufacture, while the edge region is specifically designed or modified to prevent peeling during sawing, thus achieving both manufacturing simplicity and reliability
3Volume of moving object
If vertically stacked semiconductor chips are used to reduce package size, then miniaturization is achieved, but packaging design and manufacturing limitations reduce performance
Solution Approach 1:
The patent addresses vertical stacking challenges by introducing a horizontal dimension solution through region segmentation within the insulating layer. By separating the inter-wiring insulating layer into main and edge regions, the design enables reliable vertical stacking (3D integration) while maintaining package miniaturization, as the segmentation prevents manufacturing defects that would otherwise limit performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the miniaturization and high-performance semiconductor package with improved reliability and reduced manufacturing costs by effectively separating the inter-wiring insulating layers and maintaining the integrity of the main region during the sawing process.
Implementation Method 1
forming a modified layer from a portion of the inter-wiring insulating layer arranged on the scribe lane region by using laser light
Implementation Method 2
the laser light has a transmittance equal to or greater than 90% with respect to a first portion of the passivation layer arranged on the portion of the inter-wiring insulating layer
Data Source
AI summary
The present disclosure relates to semiconductor packages. An example semiconductor package includes a substrate including an active surface and an inactive surface, a plurality of wiring structures arranged on the active surface of the substrate, an inter-wiring insulating layer arranged on the active surface of the substrate and configured to cover the plurality of wiring structures, a modified layer including both side surfaces thereof covered by the inter-wiring insulating layer and including a carbonized material, and a passivation layer arranged on the inter-wiring insulating layer and the modified layer.