Semiconductor Package Warpage Control via Asymmetric Scribe Lines
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Solution Overview
Problem
The integration of multiple semiconductor devices in wafer-level packaging poses challenges due to the need for miniaturization, higher speed, and reduced transmission and insertion losses, which existing packaging and assembling techniques struggle to address effectively.
Innovation Solution
A manufacturing method involving a carrier with a de-bonding layer, where semiconductor chips are arranged in pairs on the carrier, encapsulated, and interconnected via a redistribution structure with through interconnect vias, allowing for the formation of multiple package units on a reconstructed wafer that balances scribe line regions to minimize warpage and facilitate efficient separation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor devices are integrated in wafer-level packaging, then device density and productivity are improved, but manufacturing precision deteriorates due to warpage
Solution Approach 1:
The patent applies asymmetry by intentionally creating an uneven distribution of scribe line regions across the wafer. Specifically, the number of scribe line regions in a first direction is made different from the number in a second perpendicular direction. This asymmetric arrangement compensates for differential warpage forces, balancing the overall warpage of the wafer and improving manufacturing precision during the packaging process
2Manufacturing precision
If scribe line regions are minimized for efficient separation, then manufacturing precision improves, but device complexity increases due to packaging constraints
Solution Approach 1:
The patent applies local quality by creating non-uniform scribe line region distributions in different areas of the wafer. The scribe line regions are strategically positioned with varying numbers in different directions, allowing for efficient separation in critical areas while managing warpage in other regions. This localized optimization enables both precise separation and controlled warpage without requiring overly complex packaging structures
Data Source
AI summary
A manufacturing method of a semiconductor package includes the following steps. Semiconductor chips are disposed on a carrier. The semiconductor chips are grouped in a plurality of package units. The semiconductor chips are encapsulated in an encapsulant to form a reconstructed wafer. A redistribution structure is formed on the encapsulant. The redistribution structure electrically connects the semiconductor chips within a same package unit of the plurality of package units. The individual package units are separated by cutting through the reconstructed wafer along scribe line regions. In the reconstructed wafer, the plurality of package units are arranged so as to balance the number of scribe line regions extending across opposite halves of the reconstructed wafer in a first direction with respect to the number of scribe line regions extending across opposite halves of the reconstructed wafer in a second direction perpendicular to the first direction.