Semiconductor Package Redistribution Layout Against Seed Layer Delamination

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Solution Overview

Problem

The semiconductor industry faces challenges in achieving high integration density and preventing delamination of seed layers in semiconductor packages, particularly due to copper diffusion during the reflow process in Package-on-Package (PoP) technology.

Innovation Solution

The solution involves forming a first redistribution structure with redistribution lines and vias, where the first via is shorter than the second via, and using conductive connectors that are offset from the first via to prevent intermetallic compound (IMC) formation that could cause delamination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conductive connectors are aligned with vias to enable copper diffusion during reflow, then electrical connection is improved, but seed layer delamination occurs due to excessive IMC formation

Engineering Contradiction:
Improveelectrical connectionVSAvoidseed layer adhesion
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent applies local quality by creating different via structures in different regions: first vias are shorter and prevent IMC extension, while second vias are longer and allow controlled copper diffusion. This localized differentiation resolves the contradiction by enabling electrical connection where needed while preventing delamination in critical areas.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the via structure into two distinct types (first vias and second vias) with different lengths and functions. First vias are designed to prevent IMC extension laterally, while second vias allow controlled copper diffusion. This segmentation allows simultaneous achievement of electrical connection and seed layer protection.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If minimum feature size is reduced to increase integration density, then component density is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improveintegration densityVSAvoidfeature size control
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent changes the parameter of via length to differentiate functionality within the metallization structure. By varying via length rather than uniformly reducing all feature sizes, the patent achieves improved integration density while maintaining manufacturable precision levels for critical features.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively prevents copper diffusion from the metallization patterns to the seed layers, thereby avoiding delamination and improving the reliability of the semiconductor packages.

Implementation Method 1

an intermetallic compound (IMC) formed during reflow

Methodology Applied
Scientific EffectIntermetallic compound formation:

Implementation Method 2

copper is diffused from the second via

Methodology Applied
Scientific EffectCopper diffusion: Diffusion

Data Source

PatentUS12255184B2Semiconductor packages and methods of forming the same
Publication Date: 2025.03.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12255184B2 patent drawing
  • US12255184B2 patent drawing
  • US12255184B2 patent drawing

AI summary

A device includes a first redistribution structure comprising a first conductive line and a second conductive line. An integrated circuit die is attached to the first redistribution structure. A first via is coupled to the first conductive line on a first side, and a first conductive connector is coupled to the first conductive line on a second side opposite the first side. A second via is coupled to the second conductive line on the first side, and a second conductive connector is coupled to the second conductive line on the second side. The first via directly contacts the first conductive line without directly contacting the first conductive connector. The second via directly contacts the second conductive line and directly contacts the second conductive connector.