Semiconductor Package Segmented Encapsulation for Heat Dissipation and Yield
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Solution Overview
Problem
High-speed semiconductor package designs face challenges in heat dissipation and yield loss due to the limitations of both molding and non-molding solutions, where molding provides better heat dissipation but results in yield loss during chip-on-wafer operations, and non-molding lacks molding compound, leading to poor heat dissipation and reliability issues.
Innovation Solution
A semiconductor package structure that includes a substrate with a first semiconductor die encapsulated by a molding compound and a second die encapsulated by an underfill, where the underfill has a different filler size and material composition compared to the molding compound, allowing for improved heat dissipation and reduced yield loss by enabling the screening of defective dies before attaching the second die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If molding solution is used to encapsulate high-speed application dies, then heat dissipation is improved, but yield loss occurs during chip-on-wafer operations
Solution Approach 1:
The package structure is segmented into two distinct encapsulation regions: a first encapsulation region with molding compound for the logic die, and a second encapsulation region with underfill material for the high-speed application die. This segmentation allows each region to be optimized independently - the molding compound provides heat dissipation for the logic die while the underfill protects the high-speed die without requiring early mounting that would cause yield loss.
Solution Approach 2:
Different encapsulation materials are applied to different regions based on local requirements. The molding compound with larger filler size is used in the first encapsulation region where heat dissipation is critical, while the underfill with smaller filler size is used in the second encapsulation region where protection and thermal management for the high-speed die are needed. This local differentiation resolves the contradiction by providing appropriate encapsulation characteristics to each specific area.
2Reliability
If non-molding solution is used for high-speed application dies, then yield loss is reduced by allowing later mounting, but heat dissipation deteriorates due to absence of molding compound
Solution Approach 1:
The package employs composite encapsulation by combining two different materials - molding compound and underfill material - each with distinct properties. The molding compound provides structural support and heat dissipation for the logic die, while the underfill material provides protection and alternative thermal management for the high-speed application die. This composite approach allows the package to achieve both yield protection and adequate heat dissipation without relying on a single material solution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances heat dissipation and reduces yield loss by allowing for the detection and exclusion of defective first dies, thereby improving the reliability and efficiency of high-speed semiconductor packages.
Implementation Method 1
An average filler size in the first dielectric is substantially greater than an average filler size in the second dielectric
Data Source
AI summary
A semiconductor package structure includes a substrate, a first semiconductor die, a first dielectric, a second semiconductor die, and a second dielectric. The substrate has a first surface. The first semiconductor die is disposed on the first surface. The first dielectric encapsulates the first semiconductor die. The second semiconductor die is disposed on the first surface and adjacent to the first semiconductor die. The second dielectric encapsulates the second semiconductor die. The first dielectric is in contact with the second dielectric. An average filler size in the first dielectric is substantially greater than an average filler size in the second dielectric.