Semiconductor Package With Selective Die Etching And Isolation
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in integrating multiple differently sized chips into a single package using wafer level processing, requiring efficient isolation and interconnection methods to manage high electric fields and maintain manufacturing cost-effectiveness.
Innovation Solution
A method involving placing multiple dies over a carrier, encapsulating them with a material to form an encapsulant, selectively etching to expose specific die surfaces, and forming conductive layers to ensure isolation and interconnection, while using semiconductor pillars to manage vertical and lateral current flow orientations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If multiple differently sized chips are integrated into a single package using wafer level processing, then manufacturing cost-effectiveness is improved, but isolation and interconnection complexity increases
Solution Approach 1:
The package structure is segmented into distinct regions: an first recess for receiving a first chip, an second recess for receiving a second chip, with isolation structures between them. This segmentation allows different sized chips to be accommodated independently while maintaining electrical isolation, reducing the complexity of managing interconnections between differently sized chips.
Solution Approach 2:
Isolation structures (such as dielectric material or isolation trenches) are introduced as intermediary elements between adjacent chips. These intermediaries provide electrical isolation and mechanical separation, enabling independent handling of each chip's interconnections while maintaining overall package integration, thus reducing the complexity of cross-chip interconnection management.
2Productivity
If wafer level packaging is used to package chips directly on the wafer, then manufacturing streamlining is improved, but handling differently sized chips becomes more difficult
Solution Approach 1:
The wafer surface is structured with local variations: different recess depths, different recess positions, and different isolation structure configurations in different regions. This allows each chip location to be optimized for its specific chip size and type, enabling wafer-level processing to accommodate differently sized chips without compromising manufacturing streamlining.
Solution Approach 2:
The package structure utilizes vertical dimensionality with recesses at different depths and positions within the wafer. This three-dimensional arrangement allows differently sized chips to be accommodated in a wafer-level process by varying the recess geometry, maintaining manufacturing efficiency while handling chip size variations.
3Manufacturing precision
If the encapsulant is thinned to expose specific die surfaces, then selective electrical connection is improved, but risk of exposing unintended structures increases
Solution Approach 1:
The encapsulant is pre-configured with varying thicknesses in different regions before the thinning process. Thinner regions are positioned over areas where electrical connections are needed, while thicker regions remain over areas requiring protection. This preliminary configuration ensures that the subsequent thinning process exposes only the intended die surfaces, maintaining both precision and reliability.
Solution Approach 2:
The encapsulant layer has locally varied thickness: thinner in regions where die surfaces need to be exposed for electrical connection, and thicker in regions where die surfaces should remain protected. This local quality variation enables selective exposure during thinning, achieving precise electrical connections while preventing unintended exposure of other structures.
Data Source
AI summary
In one embodiment, a method of forming a semiconductor package includes placing a first die and a second die over a carrier. At least one of the first and the second dies are covered with an encapsulation material to form an encapsulant having a top surface and an opposite bottom surface. The encapsulant is thinned from the bottom surface to expose a first surface of the first die without exposing the second die. The exposed first surface of the first die is selectively etched to expose a second surface of the first die. A back side conductive layer is formed so as to contact the first surface. The second die is separated from the back side conductive layer by a first portion of the encapsulant.