Semiconductor Package Bonding With Self-Aligned Conductive Pillars
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Solution Overview
Problem
The challenge in semiconductor packaging is to reduce package size and enhance connection reliability while minimizing failures due to solder bump reactions with conductive pillars, especially as electronics become more compact and multi-functional, requiring highly integrated semiconductor chips with numerous input/output terminals.
Innovation Solution
The method involves forming sacrificial pads and solder bumps on a carrier substrate, conductive pillars and a protective insulating layer on a semiconductor chip, aligning and bonding the pillars to the solder bumps using surface tension to reduce gaps and prevent solder bump overflow, followed by forming redistribution layers and connection posts to create a compact and reliable package structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the gap between conductive pillars is reduced to decrease package size, then the package size is reduced, but the alignment precision between semiconductor chip and carrier substrate must be significantly improved
Solution Approach 1:
The solder bump performs self-alignment through surface tension during bonding. When the solder bump is heated and molten, its surface tension causes it to naturally align with the conductive pillar, eliminating the need for high-precision external alignment mechanisms. This self-service alignment enables reduced gaps between conductive pillars while maintaining bonding reliability.
Solution Approach 2:
The patent changes the physical state parameter of the solder bump from solid to liquid during bonding. By heating the solder bump to its melting point, its viscosity decreases and surface tension becomes dominant, enabling self-alignment. After bonding, the solder bump solidifies to provide mechanical strength. This parameter change resolves the contradiction between reduced gap size and alignment precision requirements.
2Volume of moving object
If the gap between conductive pillars is reduced, then the package size is reduced, but the risk of solder bump reaction with conductive pillar side surfaces increases
Solution Approach 1:
The patent applies a protective insulating layer to the side surfaces of conductive pillars before the bonding process. This preliminary protective action prevents direct contact and chemical reaction between the solder bump and conductive pillar side surfaces, even when gaps are reduced. The protective layer acts as a barrier that eliminates the reliability risk while allowing smaller package dimensions.
Solution Approach 2:
The protective insulating layer serves as an intermediary substance between the solder bump and conductive pillar side surfaces. This intermediary prevents harmful direct interaction while allowing the bonding process to proceed. The protective layer is specifically applied to side surfaces that would otherwise be exposed to the solder bump in reduced-gap configurations.
3Reliability
If protective insulating layer is applied to conductive pillars, then solder bump reaction is suppressed, but the device structure becomes more complex
Solution Approach 1:
The protective insulating layer is applied selectively only to the side surfaces of conductive pillars where contact with solder bumps may occur, rather than coating entire structures. This localized application provides the necessary protection while minimizing additional structural complexity. The protective layer is precisely positioned at critical interfaces only.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces package size, enhances connection reliability, and minimizes failures by precise alignment and surface tension-based bonding, enabling efficient signal terminal accommodation in compact semiconductor packages.
Implementation Method 1
by self-aligning a semiconductor chip with fine-pitch pads by using the surface tension of a solder bump
Implementation Method 2
suppressing a phenomenon in which a solder bump reacts to a side surface of a conductive pillar of a semiconductor chip
Data Source
AI summary
A method of manufacturing a semiconductor package is provided. The method includes: forming a plurality of sacrificial pads on a carrier substrate and a plurality of sacrificial solder bumps on the plurality of sacrificial pads, respectively; forming a plurality of conductive pillars and a protective insulating layer on a semiconductor chip, the protective insulating layer surrounding a side surface of each of the plurality of conductive pillars; polishing the plurality of conductive pillars and the protective insulating layer to obtain a polished surface in which a surface of each of the plurality of conductive pillars is coplanar with a surface of the protective insulating layer; and bonding the plurality of conductive pillars to the plurality of sacrificial solder bumps, respectively.