Semiconductor Package Sense Terminals for Accurate Gate Voltage Measurement
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Solution Overview
Problem
Accurate measurement of gate-to-emitter/source voltage in semiconductor packages is hindered by parasitic inductance and resistance, which are typically present to limit di/dt and dampen internal oscillations, making conventional measurement methods either inaccurate or impractical.
Innovation Solution
Incorporating additional sense terminals and configuring the gate circuit to allow for parasitic inductance within the package, while using gate resistors to manage switching speed, allowing for accurate sensing of the gate-to-emitter/source voltage without interfering with the existing parasitic components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parasitic inductance and gate resistance are present in the power semiconductor package, then di/dt limiting and oscillation damping are achieved, but gate voltage measurement accuracy deteriorates due to voltage drop from these parasitic components
Solution Approach 1:
The gate circuit is segmented into multiple independent paths: a main gate circuit for driving the power semiconductor and a separate sensing circuit for measuring gate voltage. The sensing circuit includes dedicated sense terminals (second terminal connected to gate pad, fourth terminal connected to emitter/source pad) that carry only measurement current, separating the high-current gate drive function from the low-current voltage sensing function to eliminate measurement errors caused by parasitic voltage drops.
Solution Approach 2:
Dedicated sense terminals and sense traces are introduced as intermediaries between the gate circuit and the measurement instrument. These sense terminals (second and fourth terminals) provide a direct low-impedance path for voltage sensing that bypasses the parasitic inductance and resistance in the main power circuit, allowing accurate gate voltage measurement without interfering with the di/dt limiting function of the parasitic components.
2Stability of the object's composition
If gate resistors are integrated within the package to dampen internal oscillations, then oscillation damping is improved, but gate voltage measurement accuracy worsens due to additional voltage drop across the gate resistor
Solution Approach 1:
The gate circuit is divided into a main gate drive path containing the gate resistor for oscillation damping, and a separate sensing path that taps voltage after the gate resistor. The sensing circuit measures the actual gate-to-emitter voltage that appears across the power semiconductor device, not the voltage before the gate resistor, thereby maintaining accurate measurement despite the presence of the gate resistor in the drive circuit.
Solution Approach 2:
The sensing circuit is designed with local quality optimized for voltage measurement: high-impedance input terminals, minimal trace length, and direct connection points (second terminal at gate pad, fourth terminal at emitter/source pad) that minimize the pickup of switching noise and voltage drops from the gate resistor, allowing accurate local measurement of the gate voltage at the device terminals.
3Speed
If conventional gate voltage measurement methods are used during switching, then measurement speed is maintained, but measurement accuracy deteriorates due to voltage drop from parasitic components during the switching transient
Solution Approach 1:
The sense terminals (second and fourth terminals) are pre-configured and connected directly to the gate pad and emitter/source pad respectively, establishing a dedicated low-impedance sensing path before switching occurs. This preliminary setup ensures that during the switching transient, the voltage measurement is taken through a path that minimizes the impact of parasitic inductance and resistance, allowing accurate capture of the gate voltage waveform during fast switching events without requiring slower measurement techniques.
Data Source
AI summary
One or more additional sense terminals are added to discrete semiconductor packages, assemblies and semiconductor modules, including power semiconductor modules, to sense accurately the voltage between the gate and emitter/source of voltage-controlled chips, inside the package, assembly or module.