Semiconductor Package Serialization via Embedded Build-Up Interconnect Marks

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Solution Overview

Problem

Current semiconductor packaging methods lack efficient and cost-effective means to uniquely identify and track semiconductor die within packages, leading to potential damage of identifying marks on exterior surfaces and increased processing time for marking individual packages.

Innovation Solution

Incorporating unique identifying marks within the build-up interconnect structure of semiconductor packages, which are optically detectable and machine-readable, allowing for source wafer identification and location encoding without exposing them to external damage, and enabling simultaneous formation with existing package layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If unique identifying marks are placed on exterior surfaces of semiconductor packages, then identification and tracking are enabled, but the marks are susceptible to damage during handling and processing

Engineering Contradiction:
Improveidentification reliabilityVSAvoiddamage to identifying marks
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The identifying mark is nested within the build-up interconnect structure, specifically formed as part of a conductive layer that is embedded within the package. This nesting protects the mark from external damage while maintaining its identification function, as the mark is surrounded by the package structure rather than exposed on the exterior surface.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Loss of information

If laser marking or ink printing is used to mark semiconductor packages during back-end manufacturing, then identification is achieved, but processing time increases due to sequential marking of individual packages

Engineering Contradiction:
Improveidentification capabilityVSAvoidmarking processing time
Core Design Contradiction:
Loss of informationVSLoss of time

Solution Approach 1:

The identifying mark formation is merged with the build-up interconnect structure formation process. Both the conductive layer providing electrical functionality and the identifying mark are formed simultaneously in the same manufacturing step, eliminating the need for separate marking operations and reducing overall processing time.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The identifying mark is formed preliminarily during the build-up interconnect structure formation, before final package completion. This preliminary action ensures identification capability is established early in the manufacturing process, avoiding time-consuming post-processing marking steps.

Inventive Principle:
Principle #10Preliminary action

3Loss of information

If separate marking processes are used for semiconductor packages, then identification is achieved, but manufacturing complexity and per-package costs increase

Engineering Contradiction:
Improvetraceability informationVSAvoidmanufacturing process complexity
Core Design Contradiction:
Loss of informationVSDevice complexity

Solution Approach 1:

The build-up interconnect structure serves multiple functions: it provides electrical connectivity and simultaneously embeds the identifying mark. This multi-functionality eliminates the need for separate marking processes, reducing manufacturing complexity and per-package costs while maintaining full traceability capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9520364B2Front side package-level serialization for packages comprising unique identifiers
Publication Date: 2016.12.13 DECA TECH USA INC
  • US9520364B2 patent drawing
  • US9520364B2 patent drawing
  • US9520364B2 patent drawing

AI summary

A method of making a semiconductor device can include providing a plurality of semiconductor die, wherein each semiconductor die comprises an active surface and a backside opposite the active surface. The method can include forming a build-up interconnect structure that extends over the active surface of each of the plurality of semiconductor die within the wafer, and forming a unique identifying mark for each of the plurality of semiconductor die as part of a layer within the build-up interconnect structure while simultaneously forming the layer of the build-up interconnect structure. The layer of the build-up interconnect structure can comprise both the unique identifying marks for each of the plurality of semiconductor die and functionality for the semiconductor device. Each unique identifying mark can convey a unique identity of its respective semiconductor die. The method can further include singulating the plurality of semiconductor die into a plurality of semiconductor devices.