Semiconductor Package With Shielding Core Plate Through Hole
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Solution Overview
Problem
Current semiconductor packaging techniques face challenges in achieving high integration density and reliability while maintaining a compact, lightweight design, requiring advanced methods to integrate multiple semiconductor chips in a limited area effectively.
Innovation Solution
The semiconductor package design includes a core plate with a through hole, interconnection layers, chip pads, and ball pads, along with an adhesive layer and insulating layers, allowing for flip-chip mounting and electrical connections, which reduces thickness and enhances reliability by facilitating heat transfer and shielding the semiconductor chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are integrated in a limited area to increase memory capacity, then integration density is improved, but manufacturing complexity and development time increase due to requirements for accurate and fine widths and spaces
Solution Approach 1:
The patent transitions from planar integration to three-dimensional stacking by placing semiconductor chips vertically one above another. Multiple chips are mounted on different levels of the substrate, with interconnection layers routing signals between levels. This vertical arrangement dramatically increases integration density without requiring finer lateral dimensions, thereby avoiding the manufacturing complexity associated with sub-micron patterning.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor chips are stacked within a compact vertical space. Each chip is positioned on top of the previous one, with interconnection layers embedded within the substrate structure. This nesting approach allows high integration density by utilizing the third dimension (vertical space) rather than requiring increased lateral area or finer feature sizes.
2Volume of moving object
If advanced packaging techniques are used to achieve smaller and lighter products, then product size and weight are reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent divides the packaging structure into distinct functional segments: semiconductor chips, interconnection layers, insulating layers, and substrate components. Each segment is manufactured separately using standard processes, then assembled through vertical stacking. This segmentation allows each component to be optimized independently and simplifies the overall manufacturing process compared to creating a monolithic integrated structure.
Solution Approach 2:
The substrate serves multiple functions simultaneously: it provides mechanical support for the stacked chips, contains interconnection layers for electrical routing, provides insulation between conductive elements, and enables vertical stacking geometry. This multi-functionality reduces the need for additional specialized components and simplifies the manufacturing process while achieving compact package size.
3Quantity of substance
If three-dimensional stacked arrangements are implemented to increase integration, then memory capacity is improved, but reliability challenges arise from increased complexity of interconnections
Solution Approach 1:
The patent introduces insulating layers as intermediary structures between conductive interconnection layers and semiconductor chips. These insulating layers provide electrical isolation, prevent short circuits, and manage thermal properties. By carefully designing the intermediary insulation structure, the patent reduces reliability risks associated with dense interconnections while maintaining high integration capacity.
Solution Approach 2:
The patent incorporates insulating layers and carefully designed interconnection structures before final assembly to prevent potential failure modes. The insulation layers are positioned in advance to prevent electrical shorts, and the vertical stacking geometry is designed to minimize stress on interconnections. This proactive design approach cushions against reliability issues before they can manifest in the final product.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables the creation of thinner, more reliable semiconductor packages with improved heat transfer and increased integration density, addressing the need for high-capacity, compact electronic products.
Implementation Method 1
an adhesive layer bonding the chip pad to the first semiconductor chip
Implementation Method 2
an insulating layer disposed between the core plate and the first semiconductor chip and between the chip pad and the at least one ball pad
Implementation Method 3
at least one through via passing through the insulating layer and the core plate and electrically connecting the at least one ball pad to the interconnection layer
Data Source
AI summary
A semiconductor package includes a first plate having a through hole therein, at least one interconnection layer disposed on a first surface of the first plate, and at least one semiconductor chip disposed on the at least one interconnection layer in a space defined by the through hole and electrically connected to the least one interconnection layer. The package further includes a second plate disposed on the at least one semiconductor chip and a second surface of the first plate on a side of the first plate opposite the first surface, and at least one conductive pad disposed on the second surface of the first plate and electrically connected to the at least one interconnection layer.