Semiconductor Package with Embedded Passives and Shielding

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Solution Overview

Problem

The increasing size of mobile displays requires larger battery capacities, leading to increased PCB sizes, and existing chip-on-board (COB) technology faces challenges with large mounting areas, high electromagnetic interference (EMI), and increased electric noise due to the distance between semiconductor chips and passive components.

Innovation Solution

A semiconductor package design featuring a resin body with embedded passive components, a connection member with redistribution layers, and an encapsulant that includes a shielding layer to reduce EMI, optimizing space and facilitating easy implementation of EMI shielding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If COB technology is used to mount components on PCB, then cost effectiveness is improved, but mounting area increases and EMI between components increases

Engineering Contradiction:
Improvecost effectivenessVSAvoidmounting area
Core Design Contradiction:
Ease of manufactureVSArea of stationary object

Solution Approach 1:

The patent merges the semiconductor chip and passive components into a single integrated package structure. The passive components are mounted on a substrate that is then bonded to the semiconductor chip, creating a compact unified structure that reduces the overall mounting area on the PCB while maintaining cost-effectiveness through integrated manufacturing processes.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements a nested structure where passive components are mounted on a substrate that is subsequently bonded to the semiconductor chip. This nesting approach allows multiple components to occupy overlapping spatial footprints, significantly reducing the total mounting area required on the PCB compared to traditional COB technology.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Ease of manufacture

If COB technology is used to mount components on PCB, then cost effectiveness is improved, but EMI between components increases

Engineering Contradiction:
Improvecost effectivenessVSAvoidEMI between components
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The patent extracts the passive components from the traditional PCB mounting environment and relocates them onto a dedicated substrate that is integrated with the semiconductor chip. This separation from the PCB plane reduces electromagnetic interference by removing components from the common ground plane that causes EMI in traditional COB configurations.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces an intermediate substrate structure that serves as a mediator between the semiconductor chip and the PCB. This substrate acts as an electromagnetic isolation layer, reducing EMI by providing a controlled impedance environment and preventing direct electromagnetic coupling between components that would occur in traditional COB mounting on PCB.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Object-affected harmful factors

If components are mounted with large spacing to reduce EMI, then EMI between components is reduced, but mounting area increases

Engineering Contradiction:
ImproveEMI between componentsVSAvoidmounting area
Core Design Contradiction:
Object-affected harmful factorsVSArea of stationary object

Solution Approach 1:

The patent transitions from a two-dimensional PCB mounting plane to a three-dimensional integrated structure. By stacking passive components on a substrate that is then bonded to the semiconductor chip in a vertical configuration, the design achieves electromagnetic isolation equivalent to large spacing while utilizing the vertical dimension to minimize the horizontal footprint on the PCB.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

4Area of stationary object

If semiconductor chip and passive component are placed close to reduce mounting area, then mounting area is reduced, but EMI between components increases

Engineering Contradiction:
Improvemounting areaVSAvoidEMI between components
Core Design Contradiction:
Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an intermediate substrate structure that serves as a mediator between the semiconductor chip and the PCB. This substrate acts as an electromagnetic isolation layer, reducing EMI by providing a controlled impedance environment and preventing direct electromagnetic coupling between components that would occur in traditional COB mounting on PCB.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design reduces the mounting area, minimizes EMI, and enhances electrical noise reduction, allowing for more compact and efficient semiconductor packaging suitable for larger battery capacities in mobile devices.

Implementation Method 1

an EMI shielding structure... a shielding layer to reduce EMI

Methodology Applied
Scientific EffectElectromagnetic shielding: Faraday Cage

Data Source

PatentUS10825775B2Semiconductor package integrating active and passive components with electromagnetic shielding
Publication Date: 2020.11.03 SAMSUNG ELECTRONICS CO LTD
  • US10825775B2 patent drawing
  • US10825775B2 patent drawing
  • US10825775B2 patent drawing

AI summary

A semiconductor package includes a support member including a resin body having a first surface and a second surface opposing each other and having a cavity, and at least one passive component embedded in the resin body and having a connection terminal exposed from the first surface; a first connection member disposed on the first surface of the resin body, and having a first redistribution layer on the first insulating layer and connected to the connection terminal; a second connection member disposed on the first connection member and covering the cavity, and having a second redistribution layer on the second insulating layer and connected to the first redistribution layer; and a semiconductor chip disposed on the second connection member in the cavity.