Semiconductor Package Insulation Structure for Solder Ball Short Prevention

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Solution Overview

Problem

Current semiconductor packages face challenges in reliability and durability due to issues such as solder ball shorts and open defects, which affect the overall performance and yield of the packaging process.

Innovation Solution

The semiconductor package incorporates a photosensitive insulating layer and organic insulating layers to fill spaces between chips and cover conductive pads, preventing shorts and improving reliability, while a method involving wafer structures, solder ball bonding, and thermal compression enhances the packaging process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If solder balls are used to connect conductive pads between chips, then electrical connectivity is achieved, but solder ball shorts and open defects occur reducing reliability

Engineering Contradiction:
Improvepackage reliabilityVSAvoidsolder ball shorts and open defects
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent introduces an organic insulating layer as an intermediary substance that selectively covers the side surfaces of conductive pads. This intermediary layer prevents direct contact between adjacent solder balls and conductive pads, eliminating the harmful short circuit effect while maintaining electrical connectivity through the intended solder ball connections.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent employs a thin film organic insulating layer that conformally covers the side surfaces of conductive pads. This thin film structure provides effective insulation against solder ball shorts while maintaining the compact package design and not interfering with the electrical connection function of the solder balls.

Inventive Principle:
Principle #30Flexible shells and thin films

2Reliability

If photosensitive insulating layer is used to fill spaces between chips, then protection against shorts is improved, but manufacturing process complexity increases

Engineering Contradiction:
Improveshort preventionVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces traditional mechanical filling methods with a photosensitive insulating layer that can be applied as a coating and then selectively removed through photoetching. This substitution allows for more precise control over where insulation is applied, filling spaces between chips effectively while enabling better integration with standard PCB manufacturing processes.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Reliability

If organic insulating layers cover conductive pads, then solder ball short prevention is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improveshort circuit preventionVSAvoidinsulating layer coverage precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent changes the chemical and physical parameters of the insulating layer by using organic materials with specific properties that allow conformal coverage of conductive pad side surfaces. This parameter change enables the insulating layer to adapt to the geometry of the conductive pads, providing reliable short prevention while reducing the need for extremely tight manufacturing tolerances.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively prevents solder ball shorts and improves the reliability and yield of the semiconductor package by using photosensitive and organic insulating layers, ensuring better connectivity and durability.

Implementation Method 1

a photosensitive insulating layer filling a space between the lower structure and the first semiconductor chip

Methodology Applied
Scientific EffectPhotopolymerisation: Photopolymerisation

Implementation Method 2

placing the wafer structure on the substrate and performing a thermal compression process to bond the solder balls on the first substrate conductive pads

Methodology Applied
Scientific EffectThermal compression:

Data Source

PatentUS20240145417A1Semiconductor package and method of fabricating the same
Publication Date: 2024.05.02 SAMSUNG ELECTRONICS CO LTD
  • US20240145417A1 patent drawing
  • US20240145417A1 patent drawing
  • US20240145417A1 patent drawing

AI summary

A semiconductor package and a method of fabricating the same. The semiconductor package includes a lower structure including a first lower conductive pad disposed on an upper surface thereof, a first semiconductor chip disposed on the lower structure, the first semiconductor chip including a first chip conductive pad disposed on a lower surface thereof, a solder ball connecting the first lower conductive pad and the first chip conductive pad, a photosensitive insulating layer filling a space between the lower structure and the first semiconductor chip, and a first organic insulating layer covering a side surface of the first chip conductive pad.