Semiconductor Package Layout for Shorter Chip-Stack Interconnects
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Solution Overview
Problem
Existing semiconductor package technologies face challenges in achieving high integration density, reduced size, and improved electrical characteristics while maintaining efficient electrical connections between stacked semiconductor chips.
Innovation Solution
A semiconductor package design featuring a substrate with specific pad arrangements and connection wire configurations, including connection wires that extend from the bottom surface of the second semiconductor chips to the substrate pads, and a mold layer that encloses the chip stack, allowing for reduced wire length and increased integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If connection wires are used to electrically connect stacked semiconductor chips to the substrate, then electrical connections are established, but the wire length increases causing degraded electrical characteristics
Solution Approach 1:
The patent transitions from horizontal wire routing to vertical connection through bumped pads on the chip bottom surface. This dimensional change allows direct electrical connection between the chip and substrate without long lateral wires, significantly reducing wire length and improving electrical characteristics while maintaining reliable electrical connection
2Quantity of substance
If multiple semiconductor chips are stacked in a single package, then integration density increases, but the package size and complexity increase
Solution Approach 1:
The patent implements vertical stacking of multiple semiconductor chips within a compact package structure, similar to nested dolls. This allows multiple chips to be integrated in a small volume by stacking them in the vertical direction, increasing integration density without significantly increasing the lateral package footprint
Solution Approach 2:
The patent utilizes the vertical dimension for chip stacking and electrical connection, moving away from planar integration. By stacking chips vertically and using bumped pads for connection, the design achieves high integration density in a compact lateral footprint, effectively trading lateral space for vertical space
3Area of stationary object
If chips are closely spaced to increase integration density, then compactness improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses vertical bump connections instead of lateral wire routing, which reduces sensitivity to lateral misalignment. The bumped pads extend vertically from the chip bottom surface, allowing for closer chip spacing while maintaining reliable electrical connection even with slight positioning variations
Data Source
AI summary
A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a chip stack on the substrate spaced apart from the first semiconductor chip and including second semiconductor chips, and a mold layer on the substrate at least partially enclosing the chip stack and the first semiconductor chip. The first semiconductor chip includes first pads on a bottom surface of the first semiconductor chip facing the substrate, and second pads on the bottom surface of the first semiconductor chip. Each of the second semiconductor chips includes a third pad on a bottom surface thereof facing the substrate. The second semiconductor chips may be electrically connected to the substrate through connection wires connecting the third pads to substrate pads in the substrate. A distance between adjacent ones of the first pads may be larger than a distance between adjacent ones of the second pads.