Stacked Semiconductor Package with Redistribution Wiring and Side Molding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing Fan-In wafer level packages face challenges in applying stack packages due to difficulties in forming redistribution wiring layers directly on Fab-Out wafers, and they are prone to cracks during solder ball test processes.
Innovation Solution
A semiconductor package design that includes a first semiconductor chip with a redistribution wiring layer, a second semiconductor chip stacked on top, and a molding member to prevent cracks, allowing for high bandwidth, high density, and excellent signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a redistribution wiring layer is formed directly on a Fab-Out wafer for Fan-In wafer level package, then signal transmission length is reduced for excellent signal integrity, but it becomes difficult to apply to stack packages
Solution Approach 1:
The package structure is segmented into multiple independent chips (first semiconductor chip, second semiconductor chip) stacked vertically. Each chip maintains its own redistribution wiring layer formed on its respective substrate, allowing the Fan-In package structure to be adapted for stack packaging by dividing the original single-substrate approach into multiple stacked substrates with individual wiring layers.
2Ease of manufacture
If solder balls are used as outer connection terminals for testing, then electrical connection is achieved, but cracks occur during the test process
Solution Approach 1:
A molding compound is introduced as an intermediary material that encapsulates the solder balls and provides mechanical support. This molding compound acts as a buffer that absorbs stress during testing, preventing cracks from propagating through the brittle solder ball connections while maintaining electrical connectivity.
Solution Approach 2:
The molding compound is applied in advance to encapsulate the solder balls before testing occurs. This pre-application of protective material cushions the solder balls against mechanical stresses and thermal shocks during subsequent testing procedures, preventing crack formation before it can occur.
Data Source
AI summary
A semiconductor package includes a first semiconductor chip including a first substrate having first and second surfaces opposite to each other, a through electrode in the first substrate, a first chip pad on the first surface and electrically connected to the through electrode, and a second chip pad on the first surface and electrically connected to a circuit element in the first substrate; a redistribution wiring layer on the first surface of the first semiconductor chip, and including a first redistribution wiring line electrically connected to the first chip pad and a second redistribution wiring line electrically connected to the second chip pad; a second semiconductor chip stacked on the second surface of the first semiconductor chip and electrically connected to the through electrode; and a molding member on side surfaces of the first and second semiconductor chips.