Semiconductor Package With Side Pads For High Capacity Memory
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Solution Overview
Problem
Conventional semiconductor packages face challenges in achieving high capacity and slimness while maintaining electrical characteristics, as vertical stacking of dies leads to yield reduction and thermal degradation, and package-on-package technologies fail to meet demands for miniaturization and slimness in solid-state drives.
Innovation Solution
A semiconductor package design that divides memory semiconductor dies into multiple chip stacks, using an integrated substrate with side pads for wire bonding, reducing wire length and heat dispersion, and integrating these stacks to maintain electrical and thermal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked dies is increased to achieve high capacity, then memory capacity is improved, but electrical characteristics are degraded and yield is reduced
Solution Approach 1:
The patent divides a large number of stacked dies into multiple separate stacks. Each stack contains a manageable number of dies (e.g., 4-8 dies per stack), ensuring that electrical characteristics are maintained within each stack while achieving high overall capacity through parallel stacking of multiple stacks on the substrate.
2Quantity of substance
If memory capacity is increased by stacking more dies, then capacity is improved, but package height is increased
Solution Approach 1:
Instead of creating one tall stack to achieve high capacity, the patent segments the dies into multiple shorter stacks arranged side-by-side on the substrate. This distributes the vertical height across multiple parallel structures, maintaining compact package height while achieving high total capacity through increased stack count.
3Ease of manufacture
If conventional packaging methods are used, then manufacturing is simplified, but demands for slimness and miniaturization cannot be satisfied
Solution Approach 1:
The patent employs multiple low-profile stacks rather than a single tall stack, achieving miniaturization and slimness goals. The segmented architecture allows standard wire bonding and packaging processes to be applied to each stack independently, maintaining manufacturing simplicity while reducing overall package volume and height.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design prevents yield reduction, reduces wire length, and effectively disperses heat, enabling high-capacity memory with maintained electrical and thermal characteristics, addressing the limitations of conventional packaging methods.
Implementation Method 1
a connecting member configured to electrically connect the memory semiconductor dies
Implementation Method 2
respect substrates are bonded by wire bonding using side pads on a side surface of an LGA package substrate
Data Source
AI summary
The semiconductor package according to the present invention comprises: an integrated substrate; a bottom chip stack, which is mounted on the integrated substrate, has multiple memory semiconductor dies stacked chip-on-chip, and takes charge of a part of the whole memory capacity; at least one top chip stack, which is mounted on the bottom package, has multiple memory semiconductor dies mounted therein, and takes charge of the rest of the whole memory capacity; an integration wire for electrically connecting the bottom chip stack and the top chip stack(s); and an integration protection member for sealing the integration wire.