Semiconductor Package Sidewall Plating for Balanced Double-Side Cooling
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Solution Overview
Problem
Existing chip embedding and packaging technologies face challenges in achieving symmetrical mounting of power electronics modules, leading to imbalanced parasitic elements and complex thermal management, especially in high-current applications.
Innovation Solution
A semiconductor package design with vertical side wall plating and symmetrical mounting allows for modular assembly, reducing parasitic inductances and enabling double-side cooling, using plated through-holes and metal layers for electrical and thermal connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If single side cooling is used in conventional packages, then manufacturing is simpler, but thermal management efficiency deteriorates
Solution Approach 1:
The patent transitions from single-side cooling to double-side cooling by utilizing both the first and second main surfaces of the encapsulant for thermal connections. This dimensional change in thermal management allows heat to be dissipated from both sides of the package, significantly improving thermal management efficiency while maintaining manufacturing feasibility through symmetrical design.
2Temperature
If asymmetrical mounting is used to achieve double side cooling, then thermal management improves, but parasitic element balancing deteriorates
Solution Approach 1:
The patent employs symmetrical mounting configuration where identical cooling structures are placed on both sides of the package. This symmetry ensures that parasitic elements such as source inductances and gate inductances remain balanced, while still achieving effective double-side cooling. The symmetrical design eliminates the parasitic imbalance issue that would arise from asymmetrical mounting arrangements.
3Reliability
If conventional embedding technology is used, then electrical connection is achieved, but parasitic inductances increase
Solution Approach 1:
The patent utilizes vertical side wall plating on the encapsulant to create electrical connections in the vertical dimension. By placing metal layers on the side walls and using plated through-holes, the electrical connection path is shortened and optimized, reducing parasitic inductances while maintaining reliable electrical connections between the integrated circuit and external circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides reduced package size, optimized parasitic element balancing, enhanced electrical performance, and efficient thermal management, facilitating modular and reliable high-current operations.
Implementation Method 1
a first metal layer placed upon at least a portion of one of the side walls of the encapsulant, the first metal layer being electrically connecting the at least one first connection terminal
Implementation Method 2
a second metal layer placed upon at least a portion of one or both of the first main surface and the second main surface of the encapsulant, the second metal layer electrically connecting the at least one second connection terminal and forming an electrically and thermally conductive connection for a heat dissipation
Data Source
AI summary
A semiconductor package comprises an integrated circuit comprising a first connection terminal and a second connection terminal; an encapsulant encapsulating at least part of the integrated circuit; a first metal layer and a second metal layer. The first metal layer is placed upon at least a portion of one of the side walls of the encapsulant. The first metal layer is electrically connecting the first connection terminal and is configured to form an electrically conductive and mechanically stable connection with a metal trace of a base plate when mounting the semiconductor package to the base plate. The second metal layer is placed upon at least a portion of one or both of the first main surface and the second main surface of the encapsulant.