Semiconductor Package Sidewall RDL for Higher I/O Density
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Solution Overview
Problem
Conventional wafer level chip scale packages (WLCSP) are limited by providing I/O connections only on the top side, restricting the number of connections and stacking options, which fails to meet the industry's need for minimal-sized packages with increased interconnectivity.
Innovation Solution
The implementation of an extended redistribution layer on the sidewall of a semiconductor die, allowing additional I/O connections and enabling vertical and horizontal stacking, thereby enhancing interconnectivity without adding manufacturing stages or using through-silicon vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If I/O connections are provided only on the top side of the package, then the package structure is simple, but the number of I/O connections is limited
Solution Approach 1:
The patent extends the redistribution layer from the top surface to the sidewall of the semiconductor die, utilizing the vertical dimension to create additional I/O connection areas. This dimensional transition allows connections to be formed on both the top surface and sidewall, effectively increasing the total number of I/O connections without proportionally increasing package footprint.
Solution Approach 2:
The patent divides the I/O connection areas into distinct regions: top surface connections and sidewall connections. This segmentation allows independent optimization of each connection area and enables different connection types (e.g., solder balls on top, wire bonds or solder bumps on sidewall) to be used in different regions.
2Adaptability or versatility
If conventional WLCSP processes are used, then manufacturing cost is low, but stacking options are limited
Solution Approach 1:
The extended redistribution layer on the sidewall serves multiple functions: it provides additional I/O connections for horizontal interconnection and creates connection points for vertical stacking. This multi-functional design allows the same structural modification to enable both increased connectivity and 3D stacking capabilities.
Solution Approach 2:
By utilizing the sidewall vertical surface for connections, the patent enables vertical stacking configurations that were not possible with top-surface-only connections. Packages can be stacked vertically through sidewall connections while maintaining horizontal connectivity, creating flexible 3D integration options.
3Area of stationary object
If package size is reduced, then space efficiency is improved, but interconnectivity options are limited
Solution Approach 1:
The patent transitions from two-dimensional top-surface connections to three-dimensional connections that utilize the sidewall vertical surface. This allows the package footprint to be minimized while maintaining or increasing the total number of connections by exploiting the vertical dimension for additional I/O terminals.
Solution Approach 2:
The extended redistribution layer acts as a thin conductive film that wraps around the sidewall of the die, providing additional connection area without significantly increasing the package volume. This thin-film approach allows high-density interconnection in a compact form factor.
Data Source
AI summary
A fan-out wafer level package includes a semiconductor die with a redistribution layer on a sidewall of the semiconductor die. A redistribution layer positioned over the die includes an extended portion that extends along the sidewall. The semiconductor die is encapsulated in a molding compound layer. The molding compound layer is positioned between the extended portion of the redistribution layer and the sidewall of the semiconductor die. Solder contacts, for electrically connecting the semiconductor device to an electronic circuit board, are positioned on the redistribution layer. The solder contacts and the sidewall of the redistribution layer can provide electrical contact on two different locations. Accordingly, the package can be used to improve interconnectivity by providing vertical and horizontal connections.