Semiconductor Package Conductive Plate Layout for Lower Signal Loss
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in integrating multiple semiconductor devices efficiently to meet demands for miniaturization, higher speed, and better electrical performance, particularly in achieving lower transmission and insertion losses.
Innovation Solution
A semiconductor package manufacturing process involving wafer-level packaging with a carrier, encapsulant, redistribution structure, and conductive pillars and plates that enhance electrical connections and signal fidelity, using materials like copper and solder for efficient integration and connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor devices are integrated at the wafer level, then productivity and miniaturization are improved, but manufacturing complexity and difficulty of achieving lower transmission loss increase
Solution Approach 1:
The patent divides the semiconductor manufacturing process into distinct modules: wafer-level packaging stage, die attachment stage, wire bonding stage, and encapsulation stage. Each module can be independently optimized and controlled, reducing overall manufacturing complexity while maintaining high integration efficiency
Solution Approach 2:
The patent introduces intermediate structures such as carrier wafers, die attach films, and wire bonds that serve as mediators between different components. These intermediaries simplify the integration process by providing standardized interfaces and reducing direct complexity between semiconductor dies and packaging structures
2Reliability
If advanced packaging techniques are used to achieve higher speed and better electrical performance, then transmission loss and insertion loss are reduced, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from planar 2D packaging to 3D vertical packaging structures, stacking semiconductor dies and interconnect structures in multiple layers. This dimensional change reduces signal path lengths and parasitic effects, improving electrical performance while organizing complexity vertically rather than horizontally
Solution Approach 2:
The patent performs preliminary actions during wafer-level processing, including pre-attaching dies to carrier wafers, pre-forming interconnect structures, and pre-establishing electrical connections before final packaging. This preliminary organization simplifies subsequent assembly steps and reduces overall packaging complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process results in improved transmission data rates and reduced manufacturing complexity while maintaining cost-effectiveness, enabling integration into larger electronic devices.
Implementation Method 1
an encapsulant laterally wrapping the dies
Implementation Method 2
conductive pillars and plates that enhance electrical connections and signal fidelity
Implementation Method 3
using materials like copper and solder for efficient integration and connectivity
Data Source
AI summary
Semiconductor package includes a pair of dies, a redistribution structure, and a conductive plate. Each die includes a contact pad. Redistribution structure is disposed on the pair of dies, and electrically connects the pair of dies. Redistribution structure includes an innermost dielectric layer, an outermost dielectric layer, and a redistribution conductive layer. Innermost dielectric layer is closer to the pair of dies. Redistribution conductive layer extends between the innermost dielectric layer and the outermost dielectric layer. Outermost dielectric layer is furthest from the pair of dies. Conductive plate is electrically connected to the contact pads of the pair of dies. Conductive plate extends over the outermost dielectric layer of the redistribution structure and over the pair of dies. Vertical projection of the conductive plate falls on spans of the dies of the pair of dies.