Semiconductor Package Layout for Shorter High-Speed Signal Paths
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Solution Overview
Problem
Chip-on-chip (CoC) packages face signal integrity issues and limited high-speed data rate capabilities due to high resistance and long transmission paths of bond wires, particularly in high-frequency applications, and the singulation process can damage the active surface of photonic dies during integration with electronic ICs.
Innovation Solution
A semiconductor package structure with a first electronic device featuring an angled lateral surface and a second electronic device disposed on its active surface, where the package is manufactured by forming a trench in a semiconductor substrate and separating it into individual devices to prevent damage during singulation, allowing for efficient integration and reduced warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to connect stacked electronic components, then electrical communication is achieved, but signal integrity deteriorates due to high resistance and long transmission path
Solution Approach 1:
The patent transitions from vertical wire bonding (3D stacking with long transmission paths) to lateral direct bonding (2D planar connection with short transmission paths). Electronic devices are bonded laterally adjacent to each other on the same substrate plane, reducing the transmission path from vertical wire bonds to short lateral traces, thereby improving signal integrity while maintaining electrical communication.
Solution Approach 2:
The patent eliminates the wire bonding intermediate structure by directly bonding electronic devices laterally adjacent to each other. This removes the wire bonds that caused high resistance and long transmission paths, replacing them with direct substrate-based electrical connections that provide shorter and lower-resistance pathways.
2Adaptability or versatility
If electronic ICs are formed in a package followed by flip-chip bonding to photonic IC, then integration is achieved, but the active surface of photonic die is damaged during singulation
Solution Approach 1:
The patent performs lateral bonding of electronic devices to photonic devices before the singulation process. By completing the integration and bonding operations while devices are still on the wafer in a multi-device array, the vulnerable photonic die active surfaces are already protected and connected before any cutting or separation operations occur, preventing damage during singulation.
Solution Approach 2:
The patent combines multiple electronic devices and photonic devices into a single integrated package structure on one substrate. This merged approach allows all devices to be processed and bonded together in bulk before singulation, eliminating the need for separate handling of individual photonic dies that would expose their active surfaces to damage during separation.
3Speed
If conventional wire bonding is used for high speed data transmission, then connection is established, but high speed data rate is prevented by high impedance from extended transmission path
Solution Approach 1:
The patent changes the transmission path geometry from vertical wire bonds extending through multiple stacked layers to lateral traces on a single substrate plane. This dimensional change reduces the transmission path length and minimizes impedance variations, enabling high-speed data transmission at rates such as 100 Gbit/s and 400 Gbit/s by eliminating the high impedance problem associated with extended vertical wire bond paths.
Data Source
AI summary
A semiconductor package structure and a method of manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first electronic device and a second electronic device. The first electronic device has an active surface and a lateral surface angled with the active surface, and the lateral surface includes a first portion and a second portion that is non-coplanar with the first portion. The second electronic device is disposed on the active surface of the first electronic device.