3D Semiconductor Package Layout for Low-Loss Signal Routing
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Solution Overview
Problem
Existing semiconductor device packages face significant transmission loss due to long conductive traces, particularly in high-frequency signal transmission, and manufacturing challenges such as uneven bond-line thickness and height differences in connection elements lead to reliability issues.
Innovation Solution
The semiconductor device package design minimizes transmission loss by using a first semiconductor device with an interconnection element encapsulated by an encapsulant, where a second semiconductor device is disposed vertically across the first, eliminating lateral signal paths, and employs a method involving planarization and precise bonding techniques to ensure coplanarity and uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If lateral conductive traces are used for signal transmission, then device layout flexibility is improved, but transmission loss increases significantly
Solution Approach 1:
The patent transitions signal transmission from lateral (2D plane) to vertical (3D stack) direction. Semiconductor devices are stacked vertically with interconnection elements extending between devices in the vertical dimension, eliminating long lateral conductive traces and reducing transmission loss while maintaining layout flexibility.
Solution Approach 2:
Interconnection elements serve as intermediaries that vertically connect stacked semiconductor devices. These intermediaries enable direct vertical signal paths through the encapsulant material, replacing inefficient lateral conductive traces and reducing transmission loss in high-frequency applications.
2Loss of energy
If semiconductor devices are stacked vertically, then transmission loss is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The carrier substrate is used to pre-position and align semiconductor devices and interconnection elements before encapsulation. This preliminary alignment action ensures coplanarity of exposed surfaces and uniform bond-line thickness, reducing the need for post-assembly precision adjustments.
Solution Approach 2:
The encapsulant material serves as an intermediary that fills spaces and accommodates minor dimensional variations between stacked devices and interconnection elements. This encapsulation process ensures coplanarity of exposed surfaces and uniform bond-line thickness, facilitating precise bonding while maintaining manufacturing feasibility.
3Manufacturing precision
If encapsulant material is used to encapsulate devices and interconnection elements, then manufacturing uniformity is improved, but signal transmission path complexity increases
Solution Approach 1:
The patent extracts signal transmission functions from complex lateral conductive trace networks and consolidates them into simplified vertical interconnection elements. This extraction eliminates the need for intricate lateral routing within the encapsulant, reducing signal path complexity while maintaining manufacturing uniformity through vertical stacking.
Data Source
AI summary
A semiconductor device package includes a first semiconductor device having a first surface, an interconnection element having a surface substantially coplanar with the first surface of the first semiconductor device, a first encapsulant encapsulating the first semiconductor device and the interconnection element, and a second semiconductor device disposed on and across the first semiconductor device and the interconnection element.