Semiconductor Package Structure With Silicon Interfaces Against Warping
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Solution Overview
Problem
The thermal expansion mismatch between molding compounds and silicon substrates in semiconductor packages leads to warping and damage as chip stacking increases, affecting device performance.
Innovation Solution
A semiconductor package structure utilizing silicon-containing surfaces and materials, such as Spin-on-Glass or Spin-on-Dielectric, to form jointing interfaces between chips, combined with conductive bumps and filling layers of high Young's modulus materials like glass or carbon fiber to enhance adhesion and rigidity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If molding compounds are used for packaging, then packaging function is achieved, but thermal expansion mismatch causes warping and damage when chip stacking increases
Solution Approach 1:
The patent changes the material parameter of the packaging compound from conventional organic molding compound to silicon-containing material (such as silicon oxide, silicon nitride, or spin-on-glass). This parameter change aligns the thermal expansion coefficient with the silicon substrate, eliminating thermal expansion mismatch and preventing warping and damage in stacked chip packages.
Solution Approach 2:
The patent employs composite material strategy by using silicon-containing materials that combine the packaging function with thermal expansion compatibility. The silicon-containing material acts as both the packaging compound and the structural support layer, creating a composite system that resolves the thermal expansion conflict between organic molding compounds and silicon substrates.
2Productivity
If chip stacking is increased to improve integration, then device capacity increases, but warping and damage occur affecting performance
Solution Approach 1:
By changing the material composition parameter to silicon-containing materials, the patent enables higher chip stacking without warping. The silicon-containing packaging compound provides thermal expansion compatibility that maintains structural integrity even when stacking height increases, thus allowing productivity improvement without sacrificing reliability.
3Ease of manufacture
If conventional molding compounds are used, then packaging is achieved, but jointing performance deteriorates due to thermal expansion mismatch
Solution Approach 1:
The patent changes the material parameter from conventional molding compound to silicon-containing material, which improves jointing performance by matching thermal expansion coefficients. This parameter change maintains ease of manufacture through spin-coating processes while significantly improving the precision and reliability of joints between stacked chips.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves jointing performance, reduces warping and damage, and maintains structural integrity by uniformly distributing stress across the package structure.
Implementation Method 1
improves jointing performance, reduces warping and damage, and maintains structural integrity by uniformly distributing stress across the package structure
Implementation Method 2
forming a first package compound structure between the first semiconductor chip and the first layer of the second semiconductor chips by spin coating
Implementation Method 3
maintains structural integrity by uniformly distributing stress across the package structure
Data Source
AI summary
A semiconductor package structure and a method for preparing the same are provided. The semiconductor package structure includes: a substrate; a first semiconductor chip located on the substrate, the first semiconductor chip having a first surface that is bare and the first surface having a silicon-containing surface; second semiconductor chip structures located on the first surface of the first semiconductor chip, the second semiconductor chip structures having second surfaces opposite to the first surface; a first package compound structure having a joint surface, the joint surface covering at least the first surface of the first semiconductor chip and the second surfaces of the second semiconductor chip structures. The joint surface has a silicon-containing surface.