Semiconductor Package With 3D Solenoid Inductor for Lower Energy Loss
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Solution Overview
Problem
Existing semiconductor packages face challenges in integrating inductors efficiently, which limits the performance of inductors due to energy loss and reduced Q factor, necessitating improvements in packaging to enhance inductor efficiency.
Innovation Solution
The integration of a 3D solenoid inductor within the semiconductor package structure, formed using portions of the metallization patterns of the redistribution and die stack structures, along with through vias, to improve inductor performance by reducing energy loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional planar inductor structures are used in semiconductor packages, then the package area is reduced, but the inductor Q factor decreases and energy loss increases
Solution Approach 1:
The patent transitions from traditional planar (2D) inductor structures to three-dimensional (3D) solenoid inductor structures. This dimensional change allows the inductor to achieve higher Q factors and lower energy loss while maintaining compact package area, as the 3D configuration provides better magnetic field confinement and reduced parasitic effects compared to planar designs
2Ease of manufacture
If traditional inductor structures are used, then the manufacturing process is simpler, but the inductor Q factor and performance are limited
Solution Approach 1:
The patent combines the inductor structure with the semiconductor package substrate and existing metallization layers. The solenoid inductor is formed by integrating conductive materials with the package substrate's redistribution layers and interconnect structures, merging multiple functions into a unified structure that achieves high Q factor without requiring separate inductor fabrication processes
Solution Approach 2:
The patent changes key structural parameters of the inductor, including using thicker conductors (e.g., copper pillars or widened trace lines), optimizing the solenoid geometry (number of turns, diameter, spacing), and selecting appropriate dielectric materials with lower loss tangents. These parameter changes directly improve the Q factor and overall inductor performance while remaining compatible with standard semiconductor manufacturing processes
Data Source
AI summary
A semiconductor package is provided. The semiconductor package includes a first die and a second die bonded to the first die. An encapsulant laterally encapsulates the second die. Through vias are disposed in the encapsulant. An interconnect structure is disposed on the second die, the through vias and the encapsulant. A redistribution structure is disposed on the interconnect structure. An inductor is embedded in the redistribution structure and the interconnect structure, wherein the inductor includes a portion of a metallization pattern of the redistribution structure and a portion of a conductive pattern of the interconnect structure. The portion of the metallization pattern of the inductor is adjacent to and substantially overlapped with the portion of the conductive pattern of the inductor. A manufacturing method of a semiconductor package is also provided.