Semiconductor Package Spacer Layout for Stress-Resistant Bonding

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Solution Overview

Problem

The mounting processes for semiconductor packages often apply heat and pressure, causing mechanical and thermal stress that can lead to damage, such as cracking, between semiconductor elements and the package substrate.

Innovation Solution

Incorporating an insulating spacer between the semiconductor elements and the package substrate to distribute and resist vertical stress, thereby preventing damage during the mounting process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If mounting processes apply heat and pressure to bond semiconductor elements to the package substrate, then bonding strength is improved, but mechanical and thermal stress causes damage such as cracking between the semiconductor elements and substrate

Engineering Contradiction:
Improvebonding strengthVSAvoidmechanical and thermal stress damage
Core Design Contradiction:
StrengthVSObject-affected harmful factors

Solution Approach 1:

An insulating spacer is positioned between the semiconductor element and package substrate before the mounting process. This spacer acts as a cushioning element that absorbs and distributes the mechanical and thermal stress applied during bonding, preventing direct transmission of stress to the semiconductor element and substrate interface, thereby avoiding cracking while maintaining bonding strength

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The insulating spacer serves as an intermediary component between the semiconductor element and package substrate. It mediates the stress transmission during mounting processes by providing a compliant interface that distributes localized stress over a larger area, preventing stress concentration that would otherwise cause damage to the bonded joints

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If semiconductor elements are mounted directly on the package substrate, then device complexity is reduced, but stress concentration at the bonding interface causes cracking and damage

Engineering Contradiction:
Improvestructure complexityVSAvoidbonding interface reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The mounting structure is segmented into three distinct components: the semiconductor element, the insulating spacer, and the package substrate. This segmentation allows the spacer to independently handle stress management functions while the element and substrate focus on their primary functions of signal processing and mechanical support, respectively, thereby improving bonding interface reliability without significantly increasing overall device complexity

Inventive Principle:
Principle #1Segmentation

3Manufacturing precision

If no spacer is used between semiconductor elements and substrate, then manufacturing precision requirements are simplified, but stress distribution is poor leading to cracking

Engineering Contradiction:
Improvealignment precisionVSAvoidstress resistance
Core Design Contradiction:
Manufacturing precisionVSStrength

Solution Approach 1:

The insulating spacer changes the mechanical parameters of the bonding interface by introducing a compliant layer with different elastic modulus and thickness. This parameter change enables better stress distribution across the bonding interface, transforming the stress field from concentrated to distributed, thereby preventing cracking while maintaining reasonable manufacturing precision requirements

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20240079250A1Semiconductor package and method of manufacturing
Publication Date: 2024.03.07 SAMSUNG ELECTRONICS CO LTD
  • US20240079250A1 patent drawing
  • US20240079250A1 patent drawing
  • US20240079250A1 patent drawing

AI summary

A method of manufacturing a semiconductor package includes; positioning a passive element on an upper insulating layer of a package substrate, wherein the upper insulating layer of the package substrate exposes upper surfaces of first substrate pads and second substrate pads, the passive element includes; electrodes on respective corners of a lower surface of the passive element, solder members respectively on the electrodes, and an insulating spacer on a central portion of the lower surface of the passive element between the solder members, and the solder members are respectively disposed on the second substrate pads. The method further includes; bonding the passive element on the package substrate through the solder members and the second substrate pads, and bonding a semiconductor device to the first substrate pads on the package substrate through conductive bumps on a lower surface of the semiconductor device, wherein the semiconductor device is laterally spaced apart from the passive element on the package substrate.