Semiconductor Package Spacer Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices on printed circuit boards shrink, parasitic capacitance between circuit wiring and devices increases, interfering with high-speed operations.
Innovation Solution
A semiconductor package design that includes a printed circuit board with a first pad portion, a semiconductor chip with a second pad portion, a coupling part, and a spacer made of conductive material, where the spacer and coupling part electrically couple the pad portions, creating a distance that separates the chip from the board by more than one but less than three times the thickness of the coupling part, reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size of semiconductor devices is reduced, then device miniaturization is achieved, but parasitic capacitance between circuit wiring and devices increases
Solution Approach 1:
A spacer structure is introduced as an intermediary element between the semiconductor device and the printed circuit board. This spacer creates physical separation and increases the distance between the device pad and the circuit wiring, thereby reducing parasitic capacitance while allowing the device itself to remain miniaturized.
Solution Approach 2:
The solution moves from a two-dimensional planar arrangement to a three-dimensional structure by adding vertical separation through the spacer. This increases the distance in the vertical dimension (Z-axis) between the device and the circuit board, reducing parasitic capacitance without increasing the horizontal footprint of the miniaturized device.
2Object-affected harmful factors
If the distance between the semiconductor chip and the printed circuit board is increased, then parasitic capacitance is reduced, but the complexity of the coupling structure increases
Solution Approach 1:
The coupling structure is segmented into distinct functional components: a spacer portion for vertical separation and a coupling portion for electrical connection. This segmentation allows each part to perform its specific function efficiently while keeping the overall structure manageable and not excessively complex.
Solution Approach 2:
The coupling structure is designed to perform multiple functions simultaneously: it provides vertical separation to reduce parasitic capacitance, maintains electrical connection between the device and circuit board, and ensures mechanical stability. This multi-functionality reduces the need for additional separate components, thereby controlling overall complexity.
3Object-affected harmful factors
If a spacer is introduced to increase distance between the chip and board, then parasitic capacitance is reduced, but the device structure becomes more complex
Solution Approach 1:
The spacer and coupling structures are merged into a single integrated component rather than separate elements. This merging reduces the total number of discrete parts, simplifies assembly, and decreases structural complexity while still achieving the desired vertical separation to reduce parasitic capacitance.
Solution Approach 2:
The coupling structure is formed using composite materials or multi-layer construction that combines different functional properties in a single structure, reducing the need for multiple separate components and thereby reducing overall structural complexity while maintaining the spacer function.
Data Source
AI summary
A semiconductor package according to an embodiment may include a printed circuit board that includes a first pad portion, a semiconductor chip that is mounted on the printed circuit board and includes a second pad portion, a coupling part that is between the first pad portion and the second pad portion, and a spacer that is between the coupling part and the first pad portion. The first pad portion and the second pad portion may be electrically coupled to each other through the coupling part and the spacer.