Semiconductor Package Stacked Chip Integration Density
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Solution Overview
Problem
The increasing difficulty in manufacturing highly-integrated semiconductor devices hinders the achievement of high integration density and performance, despite growing demands for such devices.
Innovation Solution
A semiconductor package design featuring a package substrate with a central and peripheral region, where first and second semiconductor chips are connected via conductive posts and bumps, allowing for increased integration density through a copper-plating process and a method of fabricating this package, including forming conductive posts and bumps to facilitate electrical connections between chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional semiconductor device manufacturing methods are used, then manufacturing processes remain simple, but integration density cannot be increased
Solution Approach 1:
The semiconductor device is divided into multiple separate chips (first chip, second chip, third chip) that are manufactured independently and then integrated together. This segmentation allows each chip to be optimized separately while achieving high overall integration density when combined, resolving the contradiction between simple manufacturing processes and increased integration density.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional stacking by placing chips at different vertical levels (first chip on package substrate, second chip on first chip, third chip on second chip). This dimensional change enables significantly higher integration density without increasing the footprint area, while maintaining relatively simple manufacturing processes for each individual chip.
2Quantity of substance
If more chips are integrated to increase density, then integration density improves, but manufacturing difficulty increases
Solution Approach 1:
By segmenting the device into multiple independently manufacturable chips, the patent enables high chip count without proportionally increasing manufacturing difficulty. Each chip can be produced using standard processes, and the complexity is managed through modular assembly rather than monolithic fabrication.
Solution Approach 2:
The chips are prepared in advance with predetermined connection structures (pads, conductive patterns) before assembly. This preliminary preparation of connection interfaces simplifies the final integration process, allowing multiple chips to be combined without creating excessive manufacturing complexity.
3Speed
If chips are connected with conventional methods, then electrical connections are established, but connection efficiency and operating speed are limited
Solution Approach 1:
The patent implements vertical electrical connections through stacked chip architecture, with conductive patterns extending through multiple chip layers. This three-dimensional connection approach reduces signal path lengths compared to planar connections, improving operating speed while managing connection structure complexity through systematic vertical routing.
Solution Approach 2:
The package substrate serves as an intermediary structure that facilitates electrical connections between multiple chips. It provides a common reference plane and connection interface, simplifying the establishment of electrical pathways between chips while enabling efficient signal transmission for improved operating speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances integration density and operating speed by enabling more efficient electrical connections and increased memory cells, while allowing for flexible chip design and improved manufacturing processes.
Implementation Method 1
A semiconductor package design featuring a package substrate with a central and peripheral region, where first and second semiconductor chips are connected via conductive posts and bumps, allowing for increased integration density through a copper-plating process
Data Source
AI summary
Provided are a semiconductor package, a semiconductor device provided with the same, and a method of fabricating the same. The semiconductor package may include a package substrate including a central region and a peripheral region, a first semiconductor chip provided on the package substrate, a first connection pattern provided on the central region of the package substrate to connect the package substrate electrically to the first semiconductor chip, at least one second semiconductor chip provided on the peripheral region of the package substrate and between the package substrate and the first semiconductor chip, and a second connection pattern provided on the peripheral region of the package substrate to connect the first semiconductor chip electrically to the second semiconductor chip.