Semiconductor Package Stacked Chips Nozzle Collision Avoidance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The miniaturization of semiconductor package devices is hindered by the need for a wide nozzle opening to avoid damaging the exposed active surface of stacked chips, which increases the distance between conductive elements and chips, leading to a larger footprint and reduced efficiency in manufacturing processes.
Innovation Solution
The semiconductor package device design includes a circuit layer with a conductive element of varying heights and recesses in the package body to accommodate the chip structure, allowing for closer spacing and reduced dimensions, while maintaining the exposure of electrical contacts through strategically placed openings and conductive layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a wide nozzle opening is used to avoid damaging the exposed active surface of stacked chips, then the reliability of chip handling is improved, but the distance between conductive elements and chips must be increased, leading to a larger package footprint
Solution Approach 1:
The patent transitions from a planar arrangement to a three-dimensional stacked configuration. Multiple chips are vertically stacked with conductive elements positioned at different heights and depths, allowing the nozzle to access chips from the top surface without requiring large lateral clearance. The conductive elements are embedded in the substrate at varying depths, creating vertical separation that resolves the conflict between nozzle access and compact footprint.
Solution Approach 2:
The patent implements a nested structure where conductive elements are embedded within the substrate layer, and chips are stacked vertically. The nozzle can access the topmost chip surface without colliding with conductive elements below, as they are nested at different vertical levels. This nesting approach allows compact packaging while maintaining reliable chip handling.
2Ease of operation
If the distance between conductive elements and chips is increased to accommodate nozzle operation, then the ease of chip manipulation is improved, but the compactness and integration density of the package is reduced
Solution Approach 1:
The patent utilizes vertical stacking to achieve chip manipulation ease without increasing lateral distances. The nozzle operates from the top surface in the vertical dimension, while conductive elements are positioned at different depths in the substrate. This dimensional separation maintains compact lateral integration while providing sufficient clearance for nozzle operation.
Solution Approach 2:
The patent applies different spatial arrangements to different components: chips are positioned at the top surface for easy nozzle access, while conductive elements are embedded at varying depths in the substrate. This localized differentiation allows each component to be optimally positioned for its function, achieving both ease of manipulation and high integration density.
3Area of stationary object
If conductive elements are positioned closer to chips, then the package dimensions are reduced, but the risk of collision with the nozzle during chip placement increases
Solution Approach 1:
The patent resolves the collision risk by positioning conductive elements at different vertical depths in the substrate while chips are stacked at the top surface. The nozzle operates in the vertical dimension from above, and conductive elements are embedded below, creating vertical separation that eliminates collision risk while maintaining compact lateral dimensions.
Solution Approach 2:
The patent employs asymmetric positioning where conductive elements are not uniformly distributed but are strategically placed at different depths and locations in the substrate. This asymmetric arrangement optimizes the spatial relationship between conductive elements and stacked chips, allowing compact packaging while ensuring the nozzle can access chip surfaces without collision.
Data Source
AI summary
A semiconductor package device includes a circuit layer having a top surface, a first electronic component disposed on the top surface of the circuit layer, and a first conductive element disposed on the top surface of the circuit layer, the first conductive element having a top surface. The first electronic component has an active surface and a back surface facing the top surface of the circuit layer. A distance between the active surface of the first electronic component and the top surface of the circuit layer is greater than a distance between the top surface of the first conductive element and the top surface of the circuit layer.