Semiconductor Package Stacked Chips Redistribution Substrate
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving compact size, high integration, and improved electrical characteristics, particularly in signal transmission speed and stability, due to complex bonding wire structures and wiring line complexities.
Innovation Solution
The semiconductor package design includes a substrate with stacked semiconductor chips, a redistribution substrate, and connectors that minimize the length of the redistribution pattern, allowing for efficient signal transmission and reducing wiring complexity, while also using a molding layer to mitigate stress and prevent delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If bonding wires and complex wiring structures are used to connect semiconductor chips, then electrical connections can be established, but signal transmission speed deteriorates and wiring complexity increases
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional stacked architecture with vertical interconnections. Multiple semiconductor chips are stacked vertically and connected through redistribution substrates, enabling signals to transmit through shorter vertical paths rather than long horizontal wiring routes, thus improving signal transmission speed while reducing wiring complexity.
Solution Approach 2:
Redistribution substrates are introduced as intermediary components between stacked semiconductor chips. These substrates provide standardized interconnection interfaces and simplify the wiring structure by consolidating multiple connection points, thereby reducing overall wiring complexity while maintaining fast signal transmission through optimized signal paths.
2Volume of moving object
If multiple semiconductor chips are stacked to achieve high integration, then compact size is improved, but stress concentration increases and delamination risk worsens
Solution Approach 1:
The patent modifies material parameters by selecting substrate materials with thermal expansion coefficients matched to the semiconductor chips. This parameter optimization reduces thermal stress during temperature cycling, preventing delamination while maintaining the compact stacked architecture for high integration.
Solution Approach 2:
The patent employs composite material structures in the redistribution substrates and adhesive layers, combining materials with complementary mechanical and thermal properties. This composite approach distributes stress more evenly across the stacked structure, enhancing delamination resistance while preserving the compact form factor.
3Reliability
If redistribution patterns are extended to connect stacked chips, then electrical connectivity is improved, but signal transmission stability deteriorates
Solution Approach 1:
The patent segments the redistribution pattern into multiple independent connection regions on the redistribution substrate. Each segment connects to specific chip pads, creating localized low-impedance paths. This segmentation prevents signal interference and maintains stable transmission while achieving comprehensive electrical connectivity across all stacked chips.
Data Source
AI summary
A semiconductor package including a first lower stack on a substrate and including first lower semiconductor chips, a redistribution substrate on the first lower stack, a redistribution connector electrically connecting the substrate to the redistribution substrate, a first upper stack on the redistribution substrate and including first upper semiconductor chips, a first upper connector electrically connecting the redistribution substrate to the first upper stack, a second upper stack horizontally spaced apart from the first upper stack and including second upper semiconductor chips, and a second upper connector electrically connecting the redistribution substrate to the second upper stack may be provided. The redistribution connector may be on one side of the redistribution substrate. The first upper connector may be on one side of the first upper stack. The second upper connector may be on one side of the second upper stack.