Semiconductor Package Stacked Components Space Utilization
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Solution Overview
Problem
The side-by-side arrangement of logic ICs and memory dies in semiconductor packages hinders miniaturization, and the space required for connecting wires between memory dies and substrates further restricts package miniaturization.
Innovation Solution
A semiconductor package design that includes a circuit layer with stacked components, conductive wires, and an insulating layer, where the conductive wires are accommodated in a space between the stacked components and the circuit layer, allowing for the placement of an electronic component within this space to reduce package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a side by side arrangement is adopted for logic IC and memory dies, then the package structure is simple, but the package size increases and miniaturization is hindered
Solution Approach 1:
The patent transitions from a two-dimensional side-by-side arrangement to a three-dimensional stacked arrangement, placing memory dies vertically above the logic IC. This dimensional change allows multiple components to occupy the same footprint area, significantly reducing package size while maintaining electrical connectivity through vertical wire bonds.
Solution Approach 2:
The patent implements a nested structure where memory dies are stacked vertically above the logic IC, with each layer containing the previous layer. The wire bonds are also nested within the package structure, running vertically through the stacked layers. This nesting approach maximizes space utilization and reduces the overall package volume.
2Volume of moving object
If spaces are provided for accommodating connecting wires between memory dies and substrate, then electrical connectivity is ensured, but package miniaturization is restricted
Solution Approach 1:
The wire bonds are arranged vertically in the third dimension, extending from the substrate through the stacked memory dies. This vertical arrangement eliminates the need for lateral wire routing spaces, allowing the package to be miniaturized in the planar direction while maintaining reliable electrical connections through the vertical wire bond path.
Solution Approach 2:
The wire bonds serve multiple functions: they provide electrical connectivity between layers, act as structural support for the stacked configuration, and enable heat dissipation pathways. This multi-functionality reduces the need for dedicated spaces for each function, contributing to package miniaturization while ensuring reliable connectivity.
3Volume of moving object
If stacked components are placed close to the circuit layer, then space is saved, but heat dissipation becomes difficult
Solution Approach 1:
The patent applies different local qualities to different regions of the package. The lower portion near the substrate includes heat dissipation structures and thermal pathways, while the upper portions contain the stacked memory dies. This localized approach allows heat to be efficiently managed at the source while maintaining compact overall dimensions.
Solution Approach 2:
The patent introduces intermediary structures between the stacked components and the substrate, including thermal interface materials and heat dissipation features in the substrate. These intermediaries facilitate efficient heat transfer from the stacked memory dies to the substrate, enabling effective thermal management in a compact package configuration.
4Ease of manufacture
If uniform insulating material is used to encapsulate stacked components, then manufacturing is simple, but package warpage occurs due to thermal expansion
Solution Approach 1:
The patent applies local quality by using insulating materials with different Young's modulus values in different regions of the package. The lower portion near the substrate uses material with higher stiffness to provide structural support and prevent warpage, while upper regions use materials optimized for other properties. This gradient approach maintains package flatness while remaining manufacturable.
Solution Approach 2:
The patent employs composite insulating material structures with varying mechanical properties. By combining materials with different thermal expansion coefficients and stiffness values in a layered or gradient configuration, the package achieves both manufacturability and resistance to warpage under thermal stress.
Data Source
AI summary
A semiconductor package device includes a circuit layer, a first set of stacked components, a first conductive wire, a space and an electronic component. The first set of stacked components is disposed on the circuit layer. The first conductive wire electrically connects the first set of stacked components. The space is defined between the first set of stacked components and the circuit layer. The space accommodates the first conductive wire. The electronic component is disposed in the space.