Semiconductor Package Vertical Stacked Connection Structures
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Solution Overview
Problem
Current semiconductor packages face challenges in increasing the number of external connection terminals while maintaining a small planar area, which affects performance and manufacturing costs.
Innovation Solution
The semiconductor package design incorporates a lower connection structure, an intermediate connection structure, and an upper connection structure with distinct insulating layers and conductive patterns, including vias and protective layers, to efficiently connect semiconductor chips to external terminals, utilizing different chemical compositions for the insulating layers to reduce planar area and enhance connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of external connection terminals is increased, then the performance of the semiconductor package is improved, but the planar area of the semiconductor package increases
Solution Approach 1:
The patent implements a three-dimensional stacked architecture with lower, intermediate, and upper connection structures arranged vertically. This multi-layer configuration allows multiple external connection terminals to be distributed across different vertical levels, enabling increased terminal count without proportionally increasing the planar footprint. The vertical stacking transforms a two-dimensional layout problem into a three-dimensional space utilization solution.
Solution Approach 2:
The patent employs nested connection structures where the intermediate connection structure is positioned between and connects the lower and upper connection structures. The intermediate structure includes its own insulating layers and conductive patterns that are embedded within the overall package architecture, creating a nested configuration that maximizes space utilization and enables higher terminal density within the same planar area.
2Ease of manufacture
If the planar area of the semiconductor chip is reduced, then the manufacturing cost is lowered, but the number of external connection terminals that can be secured decreases
Solution Approach 1:
By transitioning from a two-dimensional chip layout to a three-dimensional stacked architecture with multiple connection structures at different vertical levels, the patent enables the same or increased number of external connection terminals to be accommodated within a smaller planar chip area. The vertical dimension provides additional space for routing and connecting terminals without requiring proportional increases in chip footprint.
Solution Approach 2:
The patent divides the connection structure into multiple independent segments: lower connection structure, intermediate connection structure, and upper connection structure. Each segment can be independently designed and optimized, allowing the chip area to be minimized while distributing connection terminals across multiple segments at different vertical levels, thereby maintaining terminal quantity while reducing overall planar area.
3Reliability
If different chemical compositions are used for insulating layers, then the electrical paths and signal integrity are improved, but the device complexity increases
Solution Approach 1:
The patent applies different chemical compositions to different insulating layers based on their specific functional requirements. The lower insulating layer, intermediate insulating layer, and upper insulating layer can each have optimized material properties suited to their local electrical and mechanical demands. This localized optimization improves signal integrity and electrical performance without requiring a complete redesign of the entire structure, thereby managing complexity through targeted material selection.
Data Source
AI summary
A semiconductor package includes a lower connection structure, a semiconductor chip on the lower connection structure, an upper connection structure including a first conductive pattern layer on the semiconductor chip, a first insulating layer on the first conductive pattern layer, a second conductive pattern layer on the first insulating layer, a first via penetrating the first insulating layer to extend between the first conductive pattern layer and the second conductive pattern layer, and a second insulating layer extending between a side surface of the first via and the first insulating layer, and an intermediate connection structure between the lower connection structure and the upper connection structure. A chemical composition of the first insulating layer may differ from a chemical composition of the second insulating layer.