Semiconductor Package Vertical Stacking Direct Pad Bonding

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Solution Overview

Problem

The challenge lies in forming effective wiring connections between semiconductor chips with fine wiring on a printed circuit board, as the fine wiring on the semiconductor chip can be difficult to match with corresponding wiring on the printed circuit board, leading to connectivity issues.

Innovation Solution

A semiconductor package design that includes a substrate with a cavity, multiple semiconductor chips stacked vertically, and metal lines that connect the chips' pads directly without using intermediate metal lines for electrical connections, allowing for direct bonding between chips and reducing signal delays and package size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If fine wiring is formed in a semiconductor chip package, then high-performance miniaturized devices are achieved, but forming corresponding wiring on the printed circuit board becomes difficult

Engineering Contradiction:

Improvepackage sizeVSAvoidwiring connection difficulty

Core Design Contradiction:

Volume of moving objectVSEase of manufacture

Solution Approach 1:

The patent transitions from planar wiring connections to three-dimensional vertical stacking, where multiple semiconductor chips are stacked and connected through metal lines extending vertically through the package. This dimensional change allows fine wiring to be realized in the vertical dimension rather than requiring corresponding fine wiring on the printed circuit board plane.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent introduces metal lines as intermediary conductive structures that extend from the printed circuit board through the package substrate to connect with pads on semiconductor chips. These metal lines serve as intermediaries that bridge the connection between coarse PCB wiring and fine chip wiring, eliminating the need for direct fine wiring on the PCB.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If intermediate metal lines are used for electrical connections, then connectivity is achieved, but signal delays and power loss increase

Engineering Contradiction:

Improveelectrical connectivityVSAvoidsignal delay and power loss

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent extracts and eliminates unnecessary intermediate metal line connections by implementing direct pad-to-pad bonding between stacked semiconductor chips. The connection path is shortened by removing redundant intermediary conductive structures, allowing electrical connections to be made directly between corresponding pads on adjacent chips through direct bonding.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent performs preliminary bonding of pads between semiconductor chips during the chip stacking process itself, before final package assembly. This preliminary direct bonding establishes low-inductance, low-resistance electrical connections early in the manufacturing process, avoiding the need for subsequent intermediate wiring that would increase signal delay and power loss.

Inventive Principle:

Principle #10Preliminary action

3Productivity

If direct bonding between chips is implemented, then signal delays and package size are reduced, but manufacturing precision requirements increase

Engineering Contradiction:

Improvesignal transmission speedVSAvoidpad alignment precision

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The patent employs underfill material and molding compound as cushioning elements that compensate for thermal expansion differences and mechanical stresses between stacked chips. These materials provide beforehand cushioning that protects the direct bonding interfaces from stress-induced misalignment and damage, enabling precise pad-to-pad connections to be maintained under operating conditions.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The patent utilizes controlled parameter changes during the bonding process, including temperature, pressure, and bonding time, to achieve precise pad alignment and bonding. By carefully controlling these parameters, the manufacturing process can achieve the required precision for direct pad-to-pad bonding without excessive complexity.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS9966364B2Semiconductor package and method for fabricating the same

Publication Date: 2018.05.08 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor package comprising: a substrate including an external connection terminal and a cavity; a first semiconductor chip disposed in the cavity, the first semiconductor chip including a first pad and a second pad different from the first pad, the first pad and the second pad being disposed on a first surface of the first semiconductor chip; a metal line disposed on the substrate and the first semiconductor chip and electrically connecting the first pad of the first semiconductor chip with the external connection terminal of the substrate; a second semiconductor chip disposed on the first semiconductor chip, the second semiconductor chip including a third pad disposed on a second surface of the second semiconductor chip facing the first semiconductor chip; and a connection terminal electrically connecting the second pad of the first semiconductor chip with the third pad of the second semiconductor chip, the connection terminal being not electrically connected to the metal line.