Semiconductor Package Vertical Stacking Layout
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving high integration density and performance due to limited space and inefficient use of components, particularly in vertically stacking memory and controller chips.
Innovation Solution
A semiconductor package design featuring a package substrate with memory chips vertically stacked on one surface and controller chips on the opposite surface, connected by bonding wires to optimize space and enhance electrical connectivity, allowing for reduced controller chip area occupation and increased memory chip area ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If memory chips and controller chips are arranged on the same surface of the package substrate, then the layout is simple, but the integration density is low and the memory chip area ratio is reduced
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional vertical stacking configuration. Memory chips are stacked vertically on the first surface of the package substrate, while controller chips are stacked on the second surface, utilizing the vertical dimension to increase integration density without compromising layout simplicity.
2Length of moving object
If controller chips are placed on the first surface with memory chips, then the connection path is short, but the controller chip occupies excessive area reducing memory chip space
Solution Approach 1:
The patent moves controller chips from the first surface to the second surface, utilizing the vertical dimension to reduce their footprint on the memory chip surface. The connection path extends through the package substrate via bonding wires, maintaining electrical connectivity while freeing up valuable first surface area for memory chips.
Solution Approach 2:
The package substrate serves as an intermediary between memory chips on the first surface and controller chips on the second surface. Bonding wires act as intermediaries to establish electrical connections through the substrate, enabling spatial separation while maintaining functional connectivity.
3Reliability
If more bonding wires are used to connect vertically stacked chips, then the electrical connectivity is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent segments the electrical connection system into multiple independent bonding wires, each connecting specific pads between chips. This segmentation allows for targeted connectivity rather than requiring comprehensive interconnections, reducing the total number of bonding wires needed while maintaining essential electrical pathways.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances integration density and performance by efficiently utilizing space, reducing the controller chip's footprint while increasing the memory chip area, thereby meeting the demands for higher integration and performance in semiconductor devices.
Implementation Method 1
first bonding wires, each of which is provided to electrically connect at least two of the memory chips to each other, and second bonding wires, each of which is provided to electrically connect at least one of the memory chips to the package substrate
Implementation Method 2
third bonding wires, each of which is provided to electrically connect one of the controller chips to the package substrate
Data Source
AI summary
A semiconductor package is provided. The semiconductor package may include a plurality of memory chips, which are mounted on a top surface of a package substrate, and a plurality of controller chips, which are vertically stacked on at least one of top and bottom surfaces of the package substrate.