Semiconductor Package Stacking with Support Structures
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Solution Overview
Problem
The challenge lies in developing a semiconductor package that can effectively stack semiconductor chips of varying sizes while ensuring appropriate protection and minimizing package size, as different chips have different dimensions and require specific packaging solutions to maintain reliability and efficiency.
Innovation Solution
A multi-chip semiconductor device package is designed with a package substrate housing various sized semiconductor chips, utilizing support structures and different thicknesses of die attach films to securely stack and connect DRAM, memory controller, and nonvolatile memory chips, with the memory controller communicating through the package substrate wiring, and an encapsulant providing protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If semiconductor chips of different sizes are stacked together, then the package capacity and functionality are improved, but the manufacturing complexity and alignment difficulty increase
Solution Approach 1:
The package is divided into multiple layers, with each layer containing semiconductor chips of specific sizes. The first layer includes first and second semiconductor chips, the second layer includes third and fourth semiconductor chips, and the third layer includes fifth and sixth semiconductor chips. This segmentation allows different sized chips to be organized systematically, improving package capacity while managing manufacturing complexity through structured layering.
Solution Approach 2:
Semiconductor chips of varying sizes are nested within the multi-layer package structure, with smaller chips positioned on top of or alongside larger chips in different layers. This nesting approach maximizes the use of available package space and accommodates different chip sizes without significantly increasing manufacturing complexity, as each chip is placed in its designated layer position.
2Reliability
If chips are securely bonded together, then the reliability is improved, but the bonding process complexity increases
Solution Approach 1:
Die attach films with uniform material composition and controlled thickness are used to bond semiconductor chips across all layers. The die attach films provide consistent bonding properties throughout the package, improving reliability while simplifying the bonding process by using a standardized approach rather than requiring different bonding methods for different chip combinations.
Solution Approach 2:
Die attach films serve as intermediary bonding layers between semiconductor chips and between chips and the package substrate. These intermediate layers facilitate reliable bonding by providing a controlled interface that accommodates thermal expansion differences and mechanical stress, thereby improving bonding reliability without significantly increasing process complexity.
3Volume of moving object
If the package size is minimized, then the miniaturization is improved, but the space for accommodating different sized chips is reduced
Solution Approach 1:
The package utilizes a three-dimensional multi-layer structure to accommodate semiconductor chips of different sizes. By distributing chips across multiple vertical layers rather than attempting to fit all chips in a single plane, the design minimizes the horizontal package footprint while providing sufficient space for various chip sizes. This vertical stacking approach enables miniaturization without sacrificing the ability to accommodate different sized chips.
Data Source
AI summary
A semiconductor package may be composed of a variety of different types of semiconductor chips of different sizes and support structures stacked within the semiconductor package. Semiconductor chips having a larger chip size may be stacked above smaller semiconductor chips. Smaller chips may be included in a layer of the semiconductor package along with a support structure which may assist supporting upper semiconductor chips, such as during a wire bonding process connecting bonding wires to chip pads of the semiconductor chips above the support structure. Use of different thicknesses of die attach film may allow for a further reduction in height of the semiconductor package. When implemented as a package housing a memory controller, DRAM semiconductor chips and non-volatile memory chips, locating the memory controller in a lower layer of the semiconductor package facilitates usage of the package substrate as a redistribution layer to provide communications between the memory controller and the DRAM and non-volatile memory chips.