Semiconductor Package Thermal Management via Vertical Stacking
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Solution Overview
Problem
Semiconductor packages face challenges in heat dissipation and electromagnetic interference (EMI) shielding due to their compact design, leading to reduced device reliability and performance.
Innovation Solution
A semiconductor package design featuring a frame with a through-hole, a metal layer on its inner surface, a conductive layer covering the electronic component and frame, and a redistribution portion with solder balls, which includes a bonding auxiliary layer to enhance heat dissipation and EMI shielding by connecting the metal and conductive layers to a ground electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor packages are designed to be lightweight and compact, then device size is reduced, but heat dissipation performance deteriorates
Solution Approach 1:
The patent introduces a three-dimensional stacked architecture with multiple layers (first semiconductor chip, second semiconductor chip, intermediate substrate) arranged vertically. This dimensional transition from planar to vertical stacking enables improved heat dissipation by providing multiple heat conduction paths through the thickness direction, allowing heat to be conducted away from the chips through various routes including the intermediate substrate and external heat sinks, thus resolving the heat dissipation deterioration caused by compact design.
Solution Approach 2:
The patent divides the semiconductor package into multiple independent functional layers including first and second semiconductor chips, an intermediate substrate, and separate heat dissipation structures. This segmentation allows each layer to be optimized independently for both size and heat dissipation, with the intermediate substrate serving as a dedicated heat conduction pathway that does not increase the overall footprint but improves thermal management through distributed heat paths.
2Volume of moving object
If semiconductor packages are designed to be lightweight and compact, then device size is reduced, but device reliability deteriorates
Solution Approach 1:
The patent employs vertical stacking architecture that increases the number of bonding interfaces and connection points between layers. This dimensional transition creates redundant heat conduction paths and multiple attachment points, thereby improving reliability through distributed stress and heat management without increasing the planar device size. The intermediate substrate acts as a mechanical and thermal buffer that enhances overall package reliability.
3Volume of moving object
If distance between various devices is reduced due to miniaturization, then electronic product size is reduced, but EMI shielding performance deteriorates
Solution Approach 1:
The patent introduces an intermediate substrate with conductive patterns and via structures that create electromagnetic shielding in the vertical dimension. The stacked architecture with multiple conductive layers at different heights forms a three-dimensional EMI shielding network that blocks electromagnetic interference between devices more effectively than planar shielding, allowing reduced device spacing while maintaining EMI protection through vertical field containment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively improves heat dissipation and EMI shielding performance, enhancing the reliability and characteristics of semiconductor packages and electronic device modules.
Implementation Method 1
heat dissipation performance
Implementation Method 2
electrically connect
Implementation Method 3
conductive layer may include a solder material
Implementation Method 4
bonding auxiliary layer configured to assist the conductive layer in bonding
Data Source
AI summary
A semiconductor package includes a frame including a through-hole, an electronic component disposed in the through-hole, a redistribution portion disposed below the frame and the electronic component, a metal layer disposed on an inner surface of the frame, and a conductive layer disposed between the metal layer and the electronic component, and covering the frame and the electronic component.