3D Semiconductor Package Stacking via Through Interlayer Vias
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Solution Overview
Problem
Current semiconductor wafer level packaging methods face challenges in efficiently integrating multiple dies and optimizing electrical connections, leading to increased package height and reduced electrical performance.
Innovation Solution
The method involves using a carrier with a debond layer, forming through vias in sensor dies, and creating through interlayer vias (TIVs) that are electrically connected to these vias, allowing for the stacking of additional dies and redistribution layers to reduce package height and enhance electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional wafer level packaging methods are used to integrate multiple dies, then manufacturing simplicity is maintained, but package height increases and electrical performance deteriorates
Solution Approach 1:
The patent transitions from planar die arrangement to three-dimensional stacking architecture. Multiple dies are vertically stacked and interconnected through through-silicon vias (TSVs) and redistribution layers, enabling electrical connections in the vertical dimension rather than only horizontal plane, thus reducing package height while improving electrical performance
Solution Approach 2:
The patent implements nested structure where multiple dies are stacked vertically with intermediate redistribution layers and TSVs embedded within the stack. Each die is nested within a larger package structure that includes conductive interconnects and insulating layers, creating a compact multi-layer integrated configuration
2Length of stationary object
If multiple dies are stacked to reduce package height, then form factor is improved, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming TSVs, redistribution layers, and insulating structures on each die before stacking. The carrier substrate is prepared with alignment marks and conductive patterns in advance, enabling precise positioning and reducing assembly complexity during the stacking process
Solution Approach 2:
The manufacturing process is segmented into discrete stages: TSV formation on individual dies, redistribution layer deposition, die stacking on carrier, and final encapsulation. Each stage is independently optimized and can be performed using standard semiconductor fabrication equipment, making the complex 3D integration process manageable
Data Source
AI summary
A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a first redistribution layer, a first die over the first redistribution layer, a molding compound encapsulating at least one second die and at least one third die disposed on the first redistribution layer, and at least one fourth die and conductive elements connected to the first redistribution layer. Through vias of the first die are electrically connected to through interlayer vias penetrating through the molding compound and are electrically connected to the first redistribution layer. The semiconductor package may further include a second redistribution layer disposed on the molding compound and between the first die, the second die and the third die.